Time division multiplex coder

Claim 2

A time division multiplex coder for a digital transmission system having m channels with two even numbered channels being reserved for the transmission of signalling and synchronization data, where m is equal to an integer greater than four, comprising: (m-1) first sources of analOg signals; a second source of analog coder centering reference signal; first means to generate m time sequential timing signals, each of said timing signals defining the time of occurrence of a different one of said m channels; a fiRst sample and hold circuit; a second sample and hold circuit; a first coder centering correction circuit coupled to said first sample and hold circuit activated during a given one of the even numbered ones of said m timing signals, said given one of the even numbered ones of said m timing signals defining one of said two even numbered channels; a second coder centering correction circuit coupled to said second sample and hold circuit activated during a given one of the odd numbered ones of said m timing signals; a feedback coder coupled to each of said first and second sample and hold circuits and to each of said first and second coder centering correction circuits; a first multiplexer coupled to said first means, the input of said first sample and hold circuit, a selected one of the odd numbered ones of said (m-1) first sources, all the even numbered ones of said (m-1) first sources, and said second source, said first multiplexer responding to the even numbered ones of said m timing signals to couple the analog signals from said selected one of the odd numbered ones of said m first sources, said even numbered ones of said m first sources and said second source to said first sample and hold circuit; a second multiplexer coupled to said first means, said second source, the remainder of the odd numbered ones of said (m-1) first sources and the input of said second sample and hold circuit, said second multiplexer responding to the odd numbered ones of said m timing signals to couple the analog signals from said remainder of the odd numbered ones of said first sources and said second source to said second sampling and hold circuit; and an output circuit coupled to the output of said feedback coder to delay the digital information of said selected one of the odd numbered ones of said (m-1) first sources one channel time slot to that one of the odd numbered ones of said m timing signals passing the analog signal of said second source through said second multiplexer to said second sample and hold circuit so that saId two even numbered channels are available for the transmission of signalling and synchronization data.

Claim 3

A coder according to claim 1, wherein said output circuit includes a shift register coupled to the output of said feedback coder to provide said delay.

Claim 4

A coder according to claim 1, wherein said output circuit includes a shift register coupled to the output of said feedback coder, and an AND gate coupled to the output of said shift register and said first means responding to said one of the odd numbered ones of said m tIming signals to provide said delay.

Claim 5

A coder according to claim 1, further including a third source of signalling and synchronization codes; and wherein said output circuit includes a shift register coupled to the output of said feedback coder, a first AND gate coupled to the output of said shift register and said first means responding to said one of the odd numbered ones of said m timing signal to provide said delay and to provide at the output thereof the coded output of said selected one of the odd numbered ones of said (m-1) first sources, a second AND gate coupled to said third source and said first means responsive to said m timing signals defining said two even numbered channels to provide at the output thereof said signalling and synchronization codes, a third AND gate coupled to the output of said coder and said first means responsive to said m timing signals except for saId one of the odd numbered ones of said m timing signals and said m timings defining said two even numbered channels to provide at the output thereof coded output of said (m-1) analog signals other than said selected one of the odd numbered ones of said (m-1) analog signals, and an OR gate coupled to said first, second and third AND gates to provide a sequential code output for said time division multiplex coder.

Claim 6

A coder according to claim 1, wherein said first sample and hold circuit includes a first holding capacitor, a first coincidence device coupled between said first multiplexer and said first capacitor responding to even numbered ones of said m timing signals to charge said first capacitor to the amplitude of Said analog signal being processed at the time, a second coincidence device coupled to said first capacitor responding to odd numbered ones of said m timing signals to discharge said first capacitor, a first summing circuit coupled to said first capacitor and the output of said first centering correction circuit, and a first comparator coupled to the output of said first summing circuit and the feedback of said feedback coder to provide an input signal to said feedback coder during even numbered ones of said m timing signals; and said second sample and hold circuit includes a second holding capacitor, a third coincidence device coupled between said second multiplexer and said second capacitor responding to odd numbered ones of said m timing signals to charge said second capacitor to the amplitude of said analog signal being processed at the time, a fourth coincidence device coupled to said second capacitor responding to even numbered ones of said m timing signals to discharge said second capacitor, a second summing circuit coupled to said second capacitor and the output of said second centering correction circuit, and a second comparator coupled to the output of said second summing circuit and the feedback of said feedback coder to provide an input signal to said feedback coder during odd numbered ones of said m timing signals.

Claim 7

A coder according to claim 5, further including a first AND gate coupled between the output of said feedback coder and said first centering correction circuit responding to said given one of the even numbered ones of said m timing signals to activate said first centering corrEction circuit; and a second AND gate coupled between the output of said feedback coder and said second centering correction circuit responding to said given one of the odd numbered ones of said m timing signals to activate said second centering correction circuit.

Claim 8

A coder according to claim 1, further including a first AND gate coupled between the output of said feedback coder and said first centering correction circuit responding to said given one of the even numbered ones of said m timing signals to activate said first centering correction circuit; and a second AND gate coupled between the output of said feedback coder and said second centering correction circuit responding to said given one of the odd numbered ones of said m timing signals to activate said second centering correction circuit.

Claim 9

A coder according to claim 1, wherein said first multiplexer includes m/2 first coincidence devices each responding to a different one of said even numbered ones of said m timing signals; and said second multiplexer includes m/2 second coincidence devices each responding to a different one of said odd numbered ones of said m timing signals.

Claim 10

A coder according to claim 8, wherein said first sample and hold circuit includes a first holding capacitor, a first coincidence device coupled between said first multiplexer and said first capacitor responding to even numbered ones of said m timing signals to charge said first capacitor to the amplitude of said analog signal being processed at the time, a second coincidence device coupled to said first capacitor responding to odd numbered ones of said m timing signals to discharge said first capacitor, a first summing circuit coupled to said first capacitor and the output of said first centering correction circuit, and a first comparator coupled to the output of said first summing circuit and the feedback of said feedback coder to provide an input signal to said feedback coder during even numbered ones of said m timing signals; said second sample and hold circuit includes a second holding capacitor, a third coincidence device coupled between said second multiplexer and said second capacitor responding to odd numbered ones of said m timing signals to charge said second capacitor to the amplitude of said analog signal being processed at the time, a fourth coincidence device coupled to said second capacitor responding to even numbered ones of said m timing signals to discharge said second capacitor, a second summing circuit coupled to said second capacitor and the output of said second centering correction circuit, and a second comparator coupled to the output of said second summing circuit and the feedback of said feedback coder to provide an input signal to said feedback coder during odd numbered ones of said m timing signals; further including a first AND gate coupled between the output of said feedback coder and said first centering correction circuit responding to said given one of the even numbered ones of said m timing signals to activate said first centering correction circuit; a second AND gate coupled between the output of said feedback coder and said second centering correction circuit responding to said given one of the odd numbered ones of said m timing signals to activate said second centering correction circuit; and a fifth source of signalling and synchronization codes; and wherein said output circuit includes a shift register coupled to the output of said feedback coder, a third AND gate coupled to the output of said shift register and said third means responding to said one of the odd numbered ones of said m timing signals to provide said delay and to provide at the output thereof the coded output of said selected one of the odd numbered ones of said (m-1) third sources, a fourth AND gate coupled to said fifth source and said third means responsive to said m timing signals defining said two even numbered channels to provide at the output thereof said signalling and synchronization codes, a fifth AND gate coupled to the output of said coder and said third means responsive to said m timing signals except for said one of the odd numbered ones of said m timing signals and said m timings defining said two even numbered channels to provide at the output thereof coded output of said (m-1) analog signals other than said selected one of the odd numbered ones of said (m-1) analog signals, and an OR gate coupled to said third, fourth and fifth AND gates to provide a sequential code output for said time division multiplex coder.

Claim 11

A coder according to claim 1, wherein m is equal to 32; said first means generate thirty two time sequential timing signals, V0, V1, V2 . . . V29, V30 and V31 having V0, V2, V4 . . . V26, V28 and V30 as even numbered ones of said timing signals and V1, V3, V5 . . . V27, V29 and V31 as odd numbered ones of said timing signals; said two even numbered channels being defined by timing signals V0 and V16; said given one of the even numbered ones of said timing signals is V16; said given one of the odd numbered ones of said timing signals is V1; said first multiplex responds to timing signal V0 to couple the analog signal of said selected one of the odd numbered ones of said (m-1) first sources to said first sample and hold circuit; and said digital information of said selected one of the odd numbered ones of said (m-1) first sources is delayed from that one of said channels defined by timing signal V0 to that one of said channels defined by timing signal V1.