Patent US4544934A successfully refreshed from Google Patents.
US4544934A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Driving circuit for an electrostatic recording head
Assignee: Toshiba Corp
•
Filing: 1983-07-12
•
Granted: 1985-10-01
•
Expires: 2003-07-12
Abstract
Abstract The invention is a driving circuit for an electrostatic recording head which reduces the turn-on time, the storage time and the turn-off time of the driving circuit output pulses. Mutually complementary first and second transistors are connected with their collectors in common. A first driving signal is supplied via a coupling capacitor to the base of the first transistor, and is also supplied to the base of the second transistor. High voltage is supplied to the emitter of the first transistor. The output signal is obtained from the interconnection of the common collectors. The first driving signal has three sequential levels, two of which occur within the time period when the recording picture signals are supplied. The first level e 2 is the highest and occurs during the beginning portion of the recording signal and the second level e 1 is lower than e 2 and occurs during the remaining portion of the recording signal. The third level is the smallest (i.e., zero or ground level (o)) and occurs immediately after e 1 when no recording signals are supplied. A second driving signal is applied to the emitter of the second transistor. The second driving signal has two non-zero sequential levels (i.e., e 4 and e 3 ). The first level e 4 is the larger of the two and occurs at the end of e 1 and continues for a time approximately equal to or greater than T c . The second level e 3 occurs immediately after e 4 .
Inventors
- 👤 Fumio Owada
- 👤 Yoshiko Yamaguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:33
CPC Classifications
G; G01; G01D; G01D5/00; G01D5/02; G01D5/06; H; H03; H03K; H03K17/00; H03K17/04; H03K17/041; H03K17/0412; H03K17/04126; H03K17/51; H03K17/56; H03K17/60; H03K17/66; H03K17/665; H03K17/666; H03K17/667
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
244 words
A driving circuit for driving an electrostatic recording head with high voltage driving output pulses having a reduced turn-off, storage and turn-off time, comprising: mutually complementary first and second transistors, each having a base and emitter and commonly interconnected collectors; a first input terminal, for receiving a first driving signal, coupled to the base of said first transistor and to the base of said second transistor, and means for producing said first driving signal, said first driving signals corresponding to picture signals to be recorded by the recording head and having at least first and second non-zero signal levels during a period of time when the picture signals are supplied to the driving circuit, the first of said non-zero signal levels is the highest and occurs during a beginning portion of said time period; a second input terminal, for receiving a second driving signal, coupled to the emitter of said second transistor, and means for producing said second driving signal, said second driving signal having at least first and second non-zero signal levels the first non-zero signal level of said second driving signal being higher than the second non-zero signal level of said second driving signal and occuring substantially at an end portion of the second non-zero signal level of said first driving signal; a high voltage potential source coupled to the emitter of said first transistor; and an output terminal coupled to the interconnection of the collectors of said first and second transistors.
Claim 2
Dependent Claim
244 words
A driving circuit for driving an electrostatic recording head with high voltage driving output pulses having a reduced turn-off, storage and turn-off time, comprising: mutually complementary first and second transistors, each having a base and emitter and commonly interconnected collectors; a first input terminal, for receiving a first driving signal, coupled to the base of said first transistor and to the base of said second transistor, and means for producing said first driving signal, said first driving signals corresponding to picture signals to be recorded by the recording head and having at least first and second non-zero signal levels during a period of time when the picture signals are supplied to the driving circuit, the first of said non-zero signal levels is the highest and occurs during a beginning portion of said time period; a second input terminal, for receiving a second driving signal, coupled to the emitter of said second transistor, and means for producing said second driving signal, said second driving signal having at least first and second non-zero signal levels the first non-zero signal level of said second driving signal being higher than the second non-zero signal level of said second driving signal and occuring substantially at an end portion of the second non-zero signal level of said first driving signal; a high voltage potential source coupled to the emitter of said first transistor; and an output terminal coupled to the interconnection of the collectors of said first and second transistors.
Claim 3
Dependent Claim
281 words
A circuit comprising a plurality of driving circuits for driving an electrostatic recording head with high voltage driving output pulses having a reduced trun-off, storage and turn-off time, each driving circuit comprising: mutually complementary first and second transistors each having a base and emitter and commonly interconnected collectors; a first input terminal, for receiving a first driving signal, coupled to the base of said first transistor and to the base of said second transistor; means for producing said first driving signal; a second input terminal, for receiving a second driving signal, coupled to the emitter of said second transistor; means for producing said second driving signal; a third input terminal, for receiving a third driving signal, coupled in parallel with said first input terminal; a high voltage potential coupled to the emitter of said first transistor; an output terminal coupled to the interconnection of the collectors of the first and second transistors; the first driving signal corresponding to picture signals to be recorded by the recording head and having at least first and second non-zero signal levels during a period of time when the picture signals are supplied to the driving circuit, the first of said non-zero signal levels is the highest and occurs during a beginning portion of said time period; said second driving signal having at least first and second non-zero signal levels, the first non-zero signal level of said second driving signal being higher than the second non-zero signal level of said second driving signal and occuring substantially at an end portion of the second non-zero signal level of said first driving signal and said third driving signal representing either an open circuit condition or a grounded condition.
Claim 4
Dependent Claim
281 words
A circuit comprising a plurality of driving circuits for driving an electrostatic recording head with high voltage driving output pulses having a reduced trun-off, storage and turn-off time, each driving circuit comprising: mutually complementary first and second transistors each having a base and emitter and commonly interconnected collectors; a first input terminal, for receiving a first driving signal, coupled to the base of said first transistor and to the base of said second transistor; means for producing said first driving signal; a second input terminal, for receiving a second driving signal, coupled to the emitter of said second transistor; means for producing said second driving signal; a third input terminal, for receiving a third driving signal, coupled in parallel with said first input terminal; a high voltage potential coupled to the emitter of said first transistor; an output terminal coupled to the interconnection of the collectors of the first and second transistors; the first driving signal corresponding to picture signals to be recorded by the recording head and having at least first and second non-zero signal levels during a period of time when the picture signals are supplied to the driving circuit, the first of said non-zero signal levels is the highest and occurs during a beginning portion of said time period; said second driving signal having at least first and second non-zero signal levels, the first non-zero signal level of said second driving signal being higher than the second non-zero signal level of said second driving signal and occuring substantially at an end portion of the second non-zero signal level of said first driving signal and said third driving signal representing either an open circuit condition or a grounded condition.
Claim 5
Dependent Claim
34 words
The driving circuit of claim 1 wherein said first driving signal includes a third signal level, said first and second non-zero signal levels and said third signal level sequentially occur during said time period.
Claim 6
Dependent Claim
16 words
The driving circuit of claim 3 wherein said third signal level is a zero level signal.
Claim 7
Dependent Claim
30 words
The driving circuit of claim 1 wherein said end portion of the second non-zero signal level of said first driving signal occurs at an end portion of said time period.
Claim 8
Dependent Claim
34 words
The driving circuit of claim 2 wherein said first driving signal includes a third signal level, said first and second non-zero signal levels and said third signal level sequentially occur during said time period.
Claim 9
Dependent Claim
16 words
The driving circuit of claim 6 wherein said third signal level is a zero level signal.
Claim 10
Dependent Claim
30 words
The driving circuit of claim 2 wherein said end portion of the second non-zero signal level of said first driving signal occurs at an end portion of said time period.
Claim 11
Dependent Claim
260 words
In a driving circuit for producing high voltage driving output pulses for driving an electrostatic recording head, said circuit comprising: mutually complementary first and second transistors, each having a base and emitter and commonly interconnected collectors; a first input terminal, for receiving a first driving signal corresponding to picture signals to be recorded by the recording head, coupled to the base of said first transistor and to the base of said second transistor; a second input terminal, for receiving a second driving signal, coupled to the emitter of said second transistor; a high voltage potential source coupled to the emitter of said first transistor; and an output terminal coupled to the interconnection of the collectors of said first and second transistors; a method of reducing turn-on time, storage time and turn-off time of said high voltage output pulses comprising the steps of: applying said first driving signal to said first input terminal wherein said first driving signal has at least first and second non-zero signal levels during a period of time when the picture signals are supplied to the driving circuit, the first of said non-zero signal levels is the highest and occurs during a beginning portion of said time period; and, applying said second driving signal to said second input terminal wherein said second driving signal has at least first and second non-zero signal levels, the first non-zero signal level of said second driving signal being higher than the second non-zero signal level of said second driving signal and occuring substantially at an end portion of first driving signal.
Claim 12
Dependent Claim
260 words
In a driving circuit for producing high voltage driving output pulses for driving an electrostatic recording head, said circuit comprising: mutually complementary first and second transistors, each having a base and emitter and commonly interconnected collectors; a first input terminal, for receiving a first driving signal corresponding to picture signals to be recorded by the recording head, coupled to the base of said first transistor and to the base of said second transistor; a second input terminal, for receiving a second driving signal, coupled to the emitter of said second transistor; a high voltage potential source coupled to the emitter of said first transistor; and an output terminal coupled to the interconnection of the collectors of said first and second transistors; a method of reducing turn-on time, storage time and turn-off time of said high voltage output pulses comprising the steps of: applying said first driving signal to said first input terminal wherein said first driving signal has at least first and second non-zero signal levels during a period of time when the picture signals are supplied to the driving circuit, the first of said non-zero signal levels is the highest and occurs during a beginning portion of said time period; and, applying said second driving signal to said second input terminal wherein said second driving signal has at least first and second non-zero signal levels, the first non-zero signal level of said second driving signal being higher than the second non-zero signal level of said second driving signal and occuring substantially at an end portion of first driving signal.
References Cited (Backward Citations)
US3751682A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-09-30 | 1989-04-01 | 1989-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-09-30 | 1993-04-01 | 1993-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-09-30 | 1997-04-01 | 1997-10-01 | $7700.00 | Window Closed / Lapsed |