US4544916A
Expired / Lapsed
US
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Digital code translator
Assignee: Nokia Bell Labs
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Filing: 1982-08-31
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Granted: 1985-10-01
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Expires: 2002-08-31
Abstract
Abstract The most significant bits of each input word of a linear PCM signal address a read-only memory (ROM). Stored at each ROM address is a table of instruction words, one instruction word for each bit in the output word. The instruction words direct a switch to select each bit for the output word from a choice of 1, 0, or an input bit PCM compression according to a predetermined characteristic is implemented by instruction words which direct selection of the proper chord bits from 1 or 0 and the proper step bits from the input bits. A different compression characteristic may be implemented by a different set of stored instruction words. The instruction words also command selective bit inversion and selective inclusion of the bit in a parity check. Implementation of the translator with commercially available hardware is described.
Inventors
- 👤 Craig A. Sharper
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 15:07
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/30; H03M7/50; H03G; H03G7/00; H03G7/007
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
226 words
A digital code translator for translating an input PCM word according to a predetermined compression characteristic into an output PCM word having chord bits and step bits, said translation comprising: memory means (41, 141) having a multiplicity of addresses for storing at each said address a table of instruction words, address inputs (A4-A9) and instruction word outputs (Q0-Q5); means connecting a first predetermined selection of bits of said input word to said address inputs; selector switch means (45, 148, 150, 152) having instruction inputs connected to said instruction word outputs to receive said instruction words, a plurality of bits inputs (0-15), and a switch output (51, 161) for connecting a selected one of said plurality of bit inputs to said switch output according to an instruction word; means connecting a source of potential representative of a "1" inputs; means connecting a source o potential representative of a zero to a second one of said bit inputs; and means connecting a second predetermined selection of bits of said input word to others of said bit inputs, respectively; respective instruction words of said tables directing said switch to select said chord bits from among said first and second ones of said bit inputs and to select said step bits from among said others of said bit inputs according to said predetermined compression characteristic to generate said output word.
Claim 2
Dependent Claim
226 words
A digital code translator for translating an input PCM word according to a predetermined compression characteristic into an output PCM word having chord bits and step bits, said translation comprising: memory means (41, 141) having a multiplicity of addresses for storing at each said address a table of instruction words, address inputs (A4-A9) and instruction word outputs (Q0-Q5); means connecting a first predetermined selection of bits of said input word to said address inputs; selector switch means (45, 148, 150, 152) having instruction inputs connected to said instruction word outputs to receive said instruction words, a plurality of bits inputs (0-15), and a switch output (51, 161) for connecting a selected one of said plurality of bit inputs to said switch output according to an instruction word; means connecting a source of potential representative of a "1" inputs; means connecting a source o potential representative of a zero to a second one of said bit inputs; and means connecting a second predetermined selection of bits of said input word to others of said bit inputs, respectively; respective instruction words of said tables directing said switch to select said chord bits from among said first and second ones of said bit inputs and to select said step bits from among said others of said bit inputs according to said predetermined compression characteristic to generate said output word.
Claim 3
Dependent Claim
25 words
A digital code translator, as in claim 1, wherein said first predetermined selection of bits of said input word comprises the six most significant bits.
Claim 4
Dependent Claim
50 words
A digital code translator as in claim 1, additionally comprising selective bit inversion means (47, 148, 150, 152) connected to at least one bit of said instruction word outputs (Q3 and Q4) and to said switch output for inverting according to said instruction words selected bits of said output word.
Claim 5
Dependent Claim
91 words
A digital code translator as in claim 1 or 3, additionally comprising parity register means (59, 159) having a parity output (Q) connected to a third one of said bit inputs (15, P) and an input (J. K); and parity switch means (49, 152) connected to said switch output, said parity register means input and one of said instruction word outputs (Q5) for selectively connecting said selector switch output to said parity register means according to said instruction words to include designated bits of said output word in a parity check.
Claim 6
Dependent Claim
17 words
A digital code translator, as in claim 1, wherein said memory means comprises a programmable read-only memory.
Claim 7
Dependent Claim
74 words
A digital code translator as in claim 1, further comprising digital counting means (43, 143) for cyclically counting the number of bits in said output word, having a plurality of count outputs connected to said memory means to individually address the words of said tables of stored instruction words and a clock input connected to a source of clock pulses; said counting means advancing one word in a table in response to each-clock pulse.
Claim 8
Dependent Claim
40 words
a digital code translator as in claim 3, for translating an offset binary code into a compressed sign-magnitude code wherein said at least one bit of said instruction words causes said inverter means to invert each of said step bits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-09-30 | 1989-04-01 | 1989-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-09-30 | 1993-04-01 | 1993-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-09-30 | 1997-04-01 | 1997-10-01 | $7700.00 | Window Closed / Lapsed |