Patent US4543644A successfully refreshed from Google Patents.
US4543644A
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Control circuit for matrix-driven recording
Assignee: Hitachi Ltd
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Filing: 1982-09-09
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Granted: 1985-09-24
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Expires: 2002-09-09
Abstract
Abstract A control circuit is used for matrix drive recording. It includes a microprocessor, a RAM for storing data to be recorded therein, an address signal editing circuit for modifying the input addresses to the RAM, a shift register for converting the data from parallel to serial form and transferring it to a recording circuit, and a DMA controller for reading the data from the RAM and transferring it to the shift register.
Inventors
- 👤 Yasuyuki Kozima
- 👤 Kunio Sato
- 👤 Masaharu Tadauchi
- 👤 Hiroshi Suehiro
- 👤 Yasuo Inoue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:49
CPC Classifications
G; G06; G06K; G06K15/00; G06K15/02; G06K15/10
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
247 words
A control circuit for matrix drive recording comprising: a microprocessor; an address bus and a data bus; a random access memory connected to said microprocessor through said address and data buses; a multiplexer circuit having a first address input connected to said address bus to receive a first address and a second address input connected to receive a second address and having an address output connected to said random access memory for changing over said first and second addresses to said random access memory; an exclusive OR circuit having a plurality of two-input exclusive OR gates, each output of which is connected to supply a predetermined input address bit of said second address from said address bus to said multiplexer circuit, one of the two inputs of said plurality of exclusive OR gates being connected to receive one among a plurality of bits of said address bus and the other of said two inputs being connected to receive a respective one of the other bits of said address bus; a shift register connected to said data bus for inputting parallel data from said random access memory and for shifting the data sequentially to provide the data in series; and a direct memory access controller connected to said address bus for controlling data transfer from said random access memory to said shift register and for providing an acknowledge signal to said multiplexer to control the change over of said multiplexer circuit at the time of said data transfer.
Claim 2
Dependent Claim
247 words
A control circuit for matrix drive recording comprising: a microprocessor; an address bus and a data bus; a random access memory connected to said microprocessor through said address and data buses; a multiplexer circuit having a first address input connected to said address bus to receive a first address and a second address input connected to receive a second address and having an address output connected to said random access memory for changing over said first and second addresses to said random access memory; an exclusive OR circuit having a plurality of two-input exclusive OR gates, each output of which is connected to supply a predetermined input address bit of said second address from said address bus to said multiplexer circuit, one of the two inputs of said plurality of exclusive OR gates being connected to receive one among a plurality of bits of said address bus and the other of said two inputs being connected to receive a respective one of the other bits of said address bus; a shift register connected to said data bus for inputting parallel data from said random access memory and for shifting the data sequentially to provide the data in series; and a direct memory access controller connected to said address bus for controlling data transfer from said random access memory to said shift register and for providing an acknowledge signal to said multiplexer to control the change over of said multiplexer circuit at the time of said data transfer.
Claim 3
Dependent Claim
71 words
A control circuit according to claim 1, wherein said address bus carries at least eight bits designated zero to seven and said exclusive OR circuit comprises three exclusive OR gates, one input of each of said three gates being connected to the three bits five to seven of said address bus, respectively, and the other input of said three gates being connected in common to bit two of said address bus.
Claim 4
Dependent Claim
70 words
A control circuit according to claim 1, wherein said address bus carries at least eight bits designated zero to seven and said exclusive OR circuit comprises two exclusive OR gates, one input of each of said two gates being connected to the two bits six and seven of said address bus, respectively, and the other input of said gates being connected in common to bit five of said address bus.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-09-23 | 1989-03-25 | 1989-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-09-23 | 1993-03-25 | 1993-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-09-23 | 1997-03-25 | 1997-09-24 | $7700.00 | Window Closed / Lapsed |