Feed forward Darlington circuit

Claim 2

A Darlington transistor circuit stage having a pair of like conductivity bipolar transistors coupled together as output and driver devices with their collectors commonly connected, means coupling the emitter of said driver transistor to the base of said output transistor and means coupling the base of said driver transistor to an input terminal, said circuit comprising: a transistor, of complementary construction to that of said driver transistor, having a base coupled to said commonly connected collectors, a collector coupled to said emitter of said driver transistor and an emitter coupled to said base of said driver transistor.

Claim 3

The stage of claim 1 wherein said output and driver transistors are of NPN construction and said complementary transistor is of PNP construction.

Claim 4

An integrated circuit comprising: a substrate semiconductor wafer having a first surface and of a first conductivity type; a first region of the opposite conductivity type extending from said surface into said semiconductor to create an output transistor base; a second region of said opposite conductivity type closely adjacent to and separate from said first region and extending from said surface into said semiconductor to create a driver transistor base; a third region of said first conductivity type extending within the confines of said first region and part way therethrough to create an output transistor emitter; a fourth region of said first conductivity type extending within the confines of said second region and part way therethrough to create a driver transistor emitter; and means for coupling said output and driver transistor into a Darlington pair configuration whereby the relationship between said first and second regions produces a merged lateral transistor that is complementary to said output and driver transistors and said lateral transistor acts to drive said output transistor into saturation thereby lowering the voltage drop across said Darlington pair in saturation.

Claim 5

An integrated circuit comprising: a substrate semiconductor wafer having a first surface and of a first conductivity type; a first region of the opposite conductivity type extending from said surface into said semiconductor to create an output transistor base; a second region of said opposite conductivity type closely adjacent to and separate from said first region and extending from said surface into said semiconductor to create a driver transistor base; a third region of said first conductivity type extending within the confines of said first region and part way therethrough to create an output transistor emitter; a fourth region of said first conductivity type extending within the confines of said second region and part way therethrough to create a driver transistor emitter; and means for coupling said output and driver transistor into a Darlington pair configuration whereby the relationship between said first and second regions produces a merged lateral transistor that is complementary to said output and driver transistors and said lateral transistor acts to drive said output transistor into saturation thereby lowering the voltage drop across said Darlington pair in saturation.

Claim 6

The integrated circuit of claim 3 wherein said first region is contoured to surround said second region.

Claim 7

The integrated circuit of claim 3 wherein said driver transistor is provided with an additional emitter that is shorted to its base.

Claim 8

The integrated circuit of claim 5 wherein said additional emitter in said driver transistor is larger than its original emitter.

Claim 9

The integrated circuit of claim 3 wherein said semiconductor wafer includes a substrate of said opposite conductivity type with a surface layer of said one conductivity type and an isolation diffusion extends from the wafer surface through said layer to isolate a tub of said one conductivity type into which said Darlington transistors are fabricated.

Claim 10

The integrated circuit of claim 7 wherein a buried layer of said one conductivity type is interposed between said substrate semiconductor wafer and said layer.

Claim 11

The integrated circuit of claim 8 wherein said substrate semiconductor wafer is P type, said first and second regions P type and said third and fourth regions N type.