Semiconductor arrangement

Claim 2

A three-pole semiconductor arrangement for switching large currents having two transistors of the same region sequence connected together in a Darlington circuit, one of which acts as a driving transistor for the output transistor switching the current, characterized in that a further three-layer semiconductor transistor is provided with a region sequence opposite to that of the Darlington transistors, said further transistor having its central region directly connected to the base of said driving transistor, one outer region being connected to the base of the output transistor and its second outer region directly connected to the emitter of said output transistor.

Claim 3

A semiconductor arrangement as defined in claim 1, and comprising a housing in which the arrangement is positioned and which has three connections connected to the collector of said output transistor, said emitter of the output transistor and to said base of said driving transistor respectively with these connections forming the base, emitter or collector connections of the entire arrangement.

Claim 4

A semiconductor arrangement as defined in claim 1, wherein the individual components are so selected that the I B /U BE curve of the entire arrangement is substantially symmetrical to the zero point.

Claim 5

A semiconductor arrangement as defined in claim 2, wherein said arrangement is an integrated structure including a semiconductor body having two transistors, constituting said driving and output transistors, formed therein with said two transistors having a common collector region and respective base and emitter regions; and said one outer region of said further three-layer semiconductor transistor is a part of the base region of said output transistor; wherein in order to form said central region, a further region of the conductivity type of the emitter region of said output transistor is introduced into the base region of said output transistor; and that finally the said second outer region of said three-layer transistor is introduced into said further region of the conductivity type of the emitter region.

Claim 6

A semiconductor arrangement as defined in claim 4, wherein said emitter region of said output transistor and said central region of said further transistor are manufactured in a single diffusion process.

Claim 7

A semiconductor arrangement as defined in claim 1 used with an impressed control current for cutting off said output transistor which corresponds approximately to the magnitude of the impressed control current when said output transistor is switched on but which has the reverse polarity.

Claim 8

A semiconductor arrangement as defined in claim 6, wherein said control current amounts to approximately 1 to 5% of the desired output current when said output transistor is switched on.

Claim 9

A semiconductor arrangement for switching large currents comprising a drive transistor, an output transistor of the same region sequence as said drive transistor and connected to said drive transistor in a Darlington circuit so that the emitter of said drive transistor is connected to the base of said output transistor and the collectors of said drive and output transistors are connected together, and a further transistor having a three-layer region sequence opposite to said drive and said output transistors, said further transistor having its central region directly connected to the base of said drive transistor, one outer region connected to the base of said output transistor and its other outer region directly connected to the emitter of said output transistor.

Claim 10

A semiconductor arrangement for switching large currents comprising a drive transistor, an output transistor of the same region sequence as said drive transistor and connected to said drive transistor in a Darlington circuit so that the emitter of said drive transistor is connected to the base of said output transistor and the collectors of said drive and output transistors are connected together, and a further transistor having a three-layer region sequence opposite to said drive and said output transistors, said further transistor having its central region directly connected to the base of said drive transistor, one outer region connected to the base of said output transistor and its other outer region directly connected to the emitter of said output transistor.

Claim 11

A semiconductor circuit arrangement as defined in claim 8 wherein said arrangement is an integrated circuit including a semiconductor body having: a first region of a first conductivity type and constituting the common collector region of said drive transistor and said output transistor; second and third spaced regions of the opposite conductivity type forming respective pn junctions with said first region and constituting the base regions of said drive and output transistors respectively; fourth and fifth regions of said first conductivity type formed within said second and third regions respectively and constituting the emitter regions of said drive, and output transistors respectively; a sixth region of said first conductivity type, and constituting said central region, formed in said third region; and a seventh region of said opposite conductivity type formed in said sixth region and constituting said second outer region of said further transistor, said one outer region being formed by a portion of said third region.