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US4539694A
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Non-linear counting circuit
Assignee: Asulab AG
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Filing: 1983-09-23
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Granted: 1985-09-03
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Expires: 2003-09-23
Abstract
Abstract The counting circuit described issues a numerical information which is a non-linear function of the number of pulses applied to its input. The circuit comprises dividers which divide by integers K i the pulses applied to their inputs. A first selector connects the output of one of the dividers to the input of a counter in response to a first signal. The content of the counter is compared with numbers k i by comparators. The output of one of the comparators is connected to a control circuit by a second selector controlled by a second signal issued by the control circuit in response to a comparison signal.
Inventors
- 👤 Jean-Pierre Wattenhofer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 12:05
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/62
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
213 words
A non-linear counting circuit for a plurality of pulses, comprising: n dividers adapted each to receive said pulses on their input, to divide them by integers K 1 , K 2 , . . . , K n and to issue on their output a counting signal whenever K 1 , K 2 , . . . , K n pulses have been counted; a counter whose state at each instant is equal to the value of the non-linear counting function associated with the number of pulses counted; first controllable selection means for connecting the output of one of said dividers to the input of said counter in response to a first selection signal; n-1 decoding means for comparing the state of said counter with n-1 predetermined integers k 1 , k 2 , . . . , k n-1 and for each emitting a decoding signal whenever the state of said counter is equal to one of said n-1 integers; a control unit for issuing said first selection signal and a second selection signal in response to the application of a decoding signal; and second controllable selection means for connecting the output of one of said decoding means to the input of said control unit in response to said second selection signal.
Claim 2
Dependent Claim
213 words
A non-linear counting circuit for a plurality of pulses, comprising: n dividers adapted each to receive said pulses on their input, to divide them by integers K 1 , K 2 , . . . , K n and to issue on their output a counting signal whenever K 1 , K 2 , . . . , K n pulses have been counted; a counter whose state at each instant is equal to the value of the non-linear counting function associated with the number of pulses counted; first controllable selection means for connecting the output of one of said dividers to the input of said counter in response to a first selection signal; n-1 decoding means for comparing the state of said counter with n-1 predetermined integers k 1 , k 2 , . . . , k n-1 and for each emitting a decoding signal whenever the state of said counter is equal to one of said n-1 integers; a control unit for issuing said first selection signal and a second selection signal in response to the application of a decoding signal; and second controllable selection means for connecting the output of one of said decoding means to the input of said control unit in response to said second selection signal.
Claim 3
Dependent Claim
123 words
A counting circuit as in claim 1, wherein said control unit comprises a counter having a clock input for receiving said decoding signals and whose state is arranged to provide a common value to said first and second selection signals, wherein said first selection means comprises a first multiplexer having n inputs connected to the outputs of said n dividers, having a control input for receiving said first selection signal and having an output connected to the input of said counter, and wherein said second selection means comprises a second multiplexer having n-1 inputs connected to the outputs of the n-1 decoding means, having a control input for receiving said second selection signal and having an output arranged to issue said decoding signals.
Claim 4
Dependent Claim
41 words
A counting circuit as in claim 1, wherein said counter is adapted to be set in up and down counting modes in response to the state of a control signal issued by said control unit in synchronism with said selection signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-09-02 | 1989-03-04 | 1989-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-09-02 | 1993-03-04 | 1993-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-09-02 | 1997-03-04 | 1997-09-03 | $7700.00 | Window Closed / Lapsed |