US4499588A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for converting the frequency of a pulse train to a binary number
Assignee: RCA Licensing Corp
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Filing: 1982-07-28
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Granted: 1985-02-12
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Expires: 2002-07-28
Abstract
Abstract A system for converting the frequency of a pulse train to a binary number includes an output counter which converts the pulse train to the binary number. Sampling time periods are applied as pulses to a comparator through another counter. The number of desired sampling periods is set into the comparator. The comparator enables the counter during the sampling time periods and inhibits the output counter on the termination of the total sampling time periods. The output of the output counter, therefore, is a binary representation of the frequency of the incoming pulse train during the total sampling time period.
Inventors
- 👤 Craig E. Deyer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 08:58
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/62; G01; G01R; G01R23/00; G01R23/02; H; H03; H03M; H03M1/00; H03M1/12; H03M1/60
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
196 words
A system for converting the frequency of a pulse train to a binary number and providing said binary number to a computer controlled system comprising: input logic means responsive to said pulse train for providing frequency pulses; output counter means responsive to said frequency pulses for providing binary numbers representative of the number of frequency pulses received; timing means for setting sampling time periods; enabling means for selecting a desired number of said sampling time periods and for enabling said logic means during said sampling time periods whereby said counter means provides said binary number representative of the frequency of said pulse train during said sampling time periods; said enabling means including comparator means; means for setting said desired number of sampling periods into said comparator, and second counter means responsive to said timing means for providing said sampling periods to said comparator means whereby said comparator means provides an inhibit signal to said logic means between said sampling periods; and bistable enabling logic arranged between said comparator means and said logic means, whereby said bistable enabling logic enables said logic means during said sampling time periods and inhibits said logic means between sampling time periods.
Claim 2
Independent Claim
196 words
A system for converting the frequency of a pulse train to a binary number and providing said binary number to a computer controlled system comprising: input logic means responsive to said pulse train for providing frequency pulses; output counter means responsive to said frequency pulses for providing binary numbers representative of the number of frequency pulses received; timing means for setting sampling time periods; enabling means for selecting a desired number of said sampling time periods and for enabling said logic means during said sampling time periods whereby said counter means provides said binary number representative of the frequency of said pulse train during said sampling time periods; said enabling means including comparator means; means for setting said desired number of sampling periods into said comparator, and second counter means responsive to said timing means for providing said sampling periods to said comparator means whereby said comparator means provides an inhibit signal to said logic means between said sampling periods; and bistable enabling logic arranged between said comparator means and said logic means, whereby said bistable enabling logic enables said logic means during said sampling time periods and inhibits said logic means between sampling time periods.
Claim 3
Dependent Claim
21 words
The system of claim 1 wherein said means for setting includes a plurality of switches for setting numbers into said comparator.
Claim 4
Dependent Claim
29 words
The system of claim 2 wherein said second counter means is a binary counter and wherein said timing means provides pulses to said binary counter during said sampling periods.
Claim 5
Dependent Claim
51 words
The system of claim 3 further including multi-terminal logic means arranged between said timing means and said second counter, said multi-terminal logic means being conjunctively responsive to said timing means and to said bistable enabling logic whereby said second counter is set when said bistable enabling logic inhibits said logic means.
Claim 6
Dependent Claim
33 words
The system of claim 4 further including clear logic arranged between said timing means and said bistable enabling logic whereby said clear logic clears said bistable logic means between said sampling time periods.
Claim 7
Dependent Claim
17 words
The system of claim 5 wherein said clear logic and said bistable enabling logic include D-type flip-flops.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-02-12 | 1988-08-13 | 1989-02-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-02-12 | 1992-08-13 | 1993-02-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-02-12 | 1996-08-13 | 1997-02-12 | $7700.00 | Window Closed / Lapsed |