Patent US4539494A successfully refreshed from Google Patents.
US4539494A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device for use in a sense amplifier
Assignee: Fujitsu Ltd
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Filing: 1983-03-25
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Granted: 1985-09-03
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Expires: 2003-03-25
Abstract
Abstract A semiconductor device for use in a sense amplifier of a memory circuit includes a first load, a second load, third loads and first and second enhancement-type transistors. The first enhancement-type transistor is connected between the first load and the third loads and receives a data signal. The second enhancement-type transistor is connected between the second load and the third loads and receives a reference voltage. The reference voltage is compensated for by a temperature-compensating circuit so that the reference voltage is changed in accordance with a change in temperature.
Inventors
- 👤 Setsuo Kurafuji
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 12:41
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/062; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419; G11C7/14
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
304 words
A semiconductor device for amplifying a difference in potential between a storage state of a memory cell and a reference voltage, comprising: first power supply means for providing a first potential; second power supply means for providing a second potential, lower than said first potential; first amplifying means, operatively connected to the memory cell, for sensing the storage state of the memory cell and for generating a data signal with a temperature dependency; second amplifying means for producing an output signal in dependence upon the data signal and the reference voltage, comprising: first and second load means, operatively connected to said first power supply means, for providing loads; a first enhancement-type MIS transistor having a drain operatively connected to said first load means, a gate operatively connected to said first amplifying means to receive the data signal and a source; a second enhancement-type MIS transistor having a drain operatively connected to said second load means, a gate for receiving the reference voltage and a source; and third load means, operatively connected between the sources of said first and second enhancement-type MIS transistors and to said second power supply means, for providing a load; and a temperature-compensating circuit, operatively connected to said first and second power supply means and the gate of said second enhancement-type MIS transistor, for generating the reference voltage and providing temperature compensation by changing the reference voltage in accordance with changes in temperature to provide the reference voltage with a temperature dependency which is different from the temperature dependency of the data signal; and output buffer means, operatively connected to said first and second load means, for buffering the output signal to produce a buffered output signal having a level, said temperature compensating circuit compensating for changes in the level of the buffered output signal caused by the changes in temperature.
Claim 2
Dependent Claim
304 words
A semiconductor device for amplifying a difference in potential between a storage state of a memory cell and a reference voltage, comprising: first power supply means for providing a first potential; second power supply means for providing a second potential, lower than said first potential; first amplifying means, operatively connected to the memory cell, for sensing the storage state of the memory cell and for generating a data signal with a temperature dependency; second amplifying means for producing an output signal in dependence upon the data signal and the reference voltage, comprising: first and second load means, operatively connected to said first power supply means, for providing loads; a first enhancement-type MIS transistor having a drain operatively connected to said first load means, a gate operatively connected to said first amplifying means to receive the data signal and a source; a second enhancement-type MIS transistor having a drain operatively connected to said second load means, a gate for receiving the reference voltage and a source; and third load means, operatively connected between the sources of said first and second enhancement-type MIS transistors and to said second power supply means, for providing a load; and a temperature-compensating circuit, operatively connected to said first and second power supply means and the gate of said second enhancement-type MIS transistor, for generating the reference voltage and providing temperature compensation by changing the reference voltage in accordance with changes in temperature to provide the reference voltage with a temperature dependency which is different from the temperature dependency of the data signal; and output buffer means, operatively connected to said first and second load means, for buffering the output signal to produce a buffered output signal having a level, said temperature compensating circuit compensating for changes in the level of the buffered output signal caused by the changes in temperature.
Claim 3
Dependent Claim
54 words
A semiconductor device as set forth in claim 1, wherein each of said first and second load means comprises a depletion-type transistor having a drain operatively connected to said first power supply means and a commonly connected gate and source operatively connected to the drain of said first and second enhancement-type MIS transistors, respectively.
Claim 4
Dependent Claim
88 words
A semiconductor device as set forth in claim 1, wherein said output buffer means comprises: a third enhancement-type MIS transistor having a drain operatively connected to said first power supply means, a gate operatively connected to said first load means, and a source for providing the buffered output signal; and a fourth enhancement-type MIS transistor having a drain operatively connected to the source of said third enhancement-type transistor, a gate operatively connected to said second load means, and a source operatively connected to said second power supply means.
Claim 5
Dependent Claim
211 words
A semiconductor device for amplifying a difference in potential between a data signal read out of a memory cell and a reference voltage, comprising: first power supply means for providing a first potential; second power supply means for providing a second potential, lower than the first potential; first and second load means, operatively connected to said first power supply means, for providing loads; a first enhancement-type MIS transistor having a drain operatively connected to said first load means, a gate for receiving said data signal and a source; a second enhancement-type MIS transistor having a drain operatively connected to said second load means, a gate for receiving the reference voltage and a source; third load means for providing a load, comprising third and fourth enhancement-type MIS transistors connected in parallel, each having a drain operatively connected to the sources of said first and second enhancement-type MIS transistors, respectively, a gate operatively connected to said first and second load means, respectively, and a source operatively connected to said second power supply means; and a temperature-compensating circuit, operatively connected to said first and second power supply means and the gate of said second enhancement-type MIS transistor, for generating the reference voltage and changing the reference voltage in accordance with a change in temperature.
Claim 6
Dependent Claim
211 words
A semiconductor device for amplifying a difference in potential between a data signal read out of a memory cell and a reference voltage, comprising: first power supply means for providing a first potential; second power supply means for providing a second potential, lower than the first potential; first and second load means, operatively connected to said first power supply means, for providing loads; a first enhancement-type MIS transistor having a drain operatively connected to said first load means, a gate for receiving said data signal and a source; a second enhancement-type MIS transistor having a drain operatively connected to said second load means, a gate for receiving the reference voltage and a source; third load means for providing a load, comprising third and fourth enhancement-type MIS transistors connected in parallel, each having a drain operatively connected to the sources of said first and second enhancement-type MIS transistors, respectively, a gate operatively connected to said first and second load means, respectively, and a source operatively connected to said second power supply means; and a temperature-compensating circuit, operatively connected to said first and second power supply means and the gate of said second enhancement-type MIS transistor, for generating the reference voltage and changing the reference voltage in accordance with a change in temperature.
Claim 7
Dependent Claim
231 words
A semiconductor device for amplifying a difference in potential between a data signal read out of a memory cell and a reference voltage, comprising: first power supply means for providing a first potential; second power supply means for providing a second potential, lower than the first potential; first and second load means, operatively connected to said first power supply means, for providing loads; a first enhancement-type MIS transistor having a drain operatively connected to said first load means, a gate for receiving said data signal and a source; a second enhancement-type MIS transistor having a drain operatively connected to said second load means, a gate for receiving the reference voltage and a source; third load means, operatively connected between the sources of said first and second enhancement-type MIS transistors and to said second power supply means, for providing a load; and a temperature compensating circuit, comprising: a first resistor operatively connected to said first power supply means; a compensating enhancement-type MIS transistor having a drain operatively connected to said first resistor and the gate of said second enhancement-type MIS transistor, a gate, and a source operatively connected to said second power supply means; and second and third resistors, operatively connected to said first and second power supply means and the gate of said compensating enhancement-type MIS transistor, for applying a constant voltage to the gate of said compensating enhancement-type MIS transistor.
Claim 8
Dependent Claim
231 words
A semiconductor device for amplifying a difference in potential between a data signal read out of a memory cell and a reference voltage, comprising: first power supply means for providing a first potential; second power supply means for providing a second potential, lower than the first potential; first and second load means, operatively connected to said first power supply means, for providing loads; a first enhancement-type MIS transistor having a drain operatively connected to said first load means, a gate for receiving said data signal and a source; a second enhancement-type MIS transistor having a drain operatively connected to said second load means, a gate for receiving the reference voltage and a source; third load means, operatively connected between the sources of said first and second enhancement-type MIS transistors and to said second power supply means, for providing a load; and a temperature compensating circuit, comprising: a first resistor operatively connected to said first power supply means; a compensating enhancement-type MIS transistor having a drain operatively connected to said first resistor and the gate of said second enhancement-type MIS transistor, a gate, and a source operatively connected to said second power supply means; and second and third resistors, operatively connected to said first and second power supply means and the gate of said compensating enhancement-type MIS transistor, for applying a constant voltage to the gate of said compensating enhancement-type MIS transistor.
Claim 9
Dependent Claim
190 words
A semiconductor device for amplifying a difference in potential between a data signal read out of a memory cell and a reference voltage, comprising: first power supply means for providing a first potential; second power supply means for providing a second potential, lower than the first potential; first and second load means, operatively connected to said first power supply means, for providing loads; a first enhancement-type MIS transistor having a drain operatively connected to said first load means, a gate for receiving said data signal and a source; a second enhancement-type MIS transistor having a drain operatively connected to said second load means, a gate for receiving the reference voltage and a source; third load means, operatively connected between the sources of said first and second enhancement-type MIS transistors and to said second power supply means, for providing a load; and a temperature-compensating circuit, comprising: a resistor operatively connected to said first power supply means; and a depletion-type transistor having a drain operatively connected to said resistor and the gate of said second enhancement-type MIS transistor, and a gate and a source operatively connected to said second power supply means.
Claim 10
Dependent Claim
190 words
A semiconductor device for amplifying a difference in potential between a data signal read out of a memory cell and a reference voltage, comprising: first power supply means for providing a first potential; second power supply means for providing a second potential, lower than the first potential; first and second load means, operatively connected to said first power supply means, for providing loads; a first enhancement-type MIS transistor having a drain operatively connected to said first load means, a gate for receiving said data signal and a source; a second enhancement-type MIS transistor having a drain operatively connected to said second load means, a gate for receiving the reference voltage and a source; third load means, operatively connected between the sources of said first and second enhancement-type MIS transistors and to said second power supply means, for providing a load; and a temperature-compensating circuit, comprising: a resistor operatively connected to said first power supply means; and a depletion-type transistor having a drain operatively connected to said resistor and the gate of said second enhancement-type MIS transistor, and a gate and a source operatively connected to said second power supply means.
Claim 11
Dependent Claim
69 words
A semiconductor device, comprising: a memory cell for storing data, said memory cell providing a data signal containing the contents of the data stored in said memory cell; an output buffer having a negative temperature coefficient; and sense amplifier means, operatively connected between said memory cell and said output buffer, for amplifying said data signal, and comprising compensating means for compensating the negative temperature coefficient of said output buffer.
Claim 12
Dependent Claim
69 words
A semiconductor device, comprising: a memory cell for storing data, said memory cell providing a data signal containing the contents of the data stored in said memory cell; an output buffer having a negative temperature coefficient; and sense amplifier means, operatively connected between said memory cell and said output buffer, for amplifying said data signal, and comprising compensating means for compensating the negative temperature coefficient of said output buffer.
Claim 13
Dependent Claim
216 words
A semiconductor device, comprising: a memory cell for storing data, said memory cell providing a data signal containing the contents of the data stored in said memory cell; an output buffer having a negative temperature coefficient; and sense amplifier means for amplifying the data signal, comprising: first differential amplifier means, operatively connected to said memory cell, for amplifying said data signal; second differential amplifier means, operatively connected to said first differential amplifier means and said output buffer, for providing an output data signal and an inverse output data signal from the data signal amplified by said first differential amplifier means; and compensating means for compensating the negative temperature coefficient of said output buffer, comprising: first power supply means for providing a first potential; second power supply means for providing a second potential, lower than said first potential; a first resistor operatively connected to said first power supply means; an enhancement-type MIS transistor, operatively connected to said first resistor, said second differential amplifier means and said second power supply means, having a gate; and second and third resistors, operatively connected to said first and second power supply means, respectively, and operatively connected to each other and to the gate of said enhancement-type MIS transistor, for applying a constant voltage to the gate of said enhancement-type MIS transistor.
Claim 14
Dependent Claim
216 words
A semiconductor device, comprising: a memory cell for storing data, said memory cell providing a data signal containing the contents of the data stored in said memory cell; an output buffer having a negative temperature coefficient; and sense amplifier means for amplifying the data signal, comprising: first differential amplifier means, operatively connected to said memory cell, for amplifying said data signal; second differential amplifier means, operatively connected to said first differential amplifier means and said output buffer, for providing an output data signal and an inverse output data signal from the data signal amplified by said first differential amplifier means; and compensating means for compensating the negative temperature coefficient of said output buffer, comprising: first power supply means for providing a first potential; second power supply means for providing a second potential, lower than said first potential; a first resistor operatively connected to said first power supply means; an enhancement-type MIS transistor, operatively connected to said first resistor, said second differential amplifier means and said second power supply means, having a gate; and second and third resistors, operatively connected to said first and second power supply means, respectively, and operatively connected to each other and to the gate of said enhancement-type MIS transistor, for applying a constant voltage to the gate of said enhancement-type MIS transistor.
Claim 15
Dependent Claim
167 words
A semiconductor device, comprising: a memory cell for storing data, said memory cell providing a data signal containing the contents of the data stored in said memory cell; an output buffer having a negative temperature coefficient; and sense amplifier means for amplifying the data signal, comprising: first differential amplifier means, operatively connected to said memory cell, for amplifying said data signal; second differential amplifier means, operatively connected to said first differential amplifier means and said output buffer, for providing an output data signal and an inverse output data signal from said data signal amplified by said first differential amplifier means; and compensating means for compensating the negative temperature coefficient of said output buffer, comprising: first power supply means for providing a first potential; second power supply means for providing a second potential, lower than said first potential; a resistor operatively connected to said first power supply means; and a depletion-type transistor operatively connected to said resistor, said second differential amplifier means and said second power supply means.
Claim 16
Dependent Claim
167 words
A semiconductor device, comprising: a memory cell for storing data, said memory cell providing a data signal containing the contents of the data stored in said memory cell; an output buffer having a negative temperature coefficient; and sense amplifier means for amplifying the data signal, comprising: first differential amplifier means, operatively connected to said memory cell, for amplifying said data signal; second differential amplifier means, operatively connected to said first differential amplifier means and said output buffer, for providing an output data signal and an inverse output data signal from said data signal amplified by said first differential amplifier means; and compensating means for compensating the negative temperature coefficient of said output buffer, comprising: first power supply means for providing a first potential; second power supply means for providing a second potential, lower than said first potential; a resistor operatively connected to said first power supply means; and a depletion-type transistor operatively connected to said resistor, said second differential amplifier means and said second power supply means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-09-02 | 1989-03-04 | 1989-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-09-02 | 1993-03-04 | 1993-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-09-02 | 1997-03-04 | 1997-09-03 | $7700.00 | Window Closed / Lapsed |