Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
301 words
A signal translating circuit for generating plural pulse outputs in positions that are shifted time sequentially, said signal translating circuit comprising: an input terminal supplied with an input signal; first and second clock terminals supplied with first and second clock signals, respectively, said first and second clock signals having different phases from each other; plural translating stages connected in series to said input terminal, each stage including a source follower transistor having a gate, a source and a drain, said drain being connected to one of said first and second clock terminals, and a bootstrap capacitor formed between said gate and source; and a transmission gate transistor having a gate, a source and a drain, the drain of said transmission gate transistor being connected to the source of said source follower transistor, the gate of said transmission gate transistor being connected to receive an enabling potential, and the source of said transmission gate transistor being connected to the gate of the source follower transistor of a succeeding stage; plural output terminals where said plural pulse outputs appear, said output terminals being respectively connected to the sources of the source follower transistors; means for connecting said first clock terminal to the drains of said source follower transistors of alternate stages and for connecting said second clock terminal to the drains of said source follower transistors of the remaining stages; a switching device connected between each output terminal and ground and actuating means in each stage for turning on said switching device, said actuating means receiving the pulse output of the succeeding output terminal and generating a control signal in response thereto for turning on said switching device; and reset means in each stage for resetting said control signal, said reset means being controlled by the pulse output of the preceding output terminal.
Claim 2
Dependent Claim
301 words
A signal translating circuit for generating plural pulse outputs in positions that are shifted time sequentially, said signal translating circuit comprising: an input terminal supplied with an input signal; first and second clock terminals supplied with first and second clock signals, respectively, said first and second clock signals having different phases from each other; plural translating stages connected in series to said input terminal, each stage including a source follower transistor having a gate, a source and a drain, said drain being connected to one of said first and second clock terminals, and a bootstrap capacitor formed between said gate and source; and a transmission gate transistor having a gate, a source and a drain, the drain of said transmission gate transistor being connected to the source of said source follower transistor, the gate of said transmission gate transistor being connected to receive an enabling potential, and the source of said transmission gate transistor being connected to the gate of the source follower transistor of a succeeding stage; plural output terminals where said plural pulse outputs appear, said output terminals being respectively connected to the sources of the source follower transistors; means for connecting said first clock terminal to the drains of said source follower transistors of alternate stages and for connecting said second clock terminal to the drains of said source follower transistors of the remaining stages; a switching device connected between each output terminal and ground and actuating means in each stage for turning on said switching device, said actuating means receiving the pulse output of the succeeding output terminal and generating a control signal in response thereto for turning on said switching device; and reset means in each stage for resetting said control signal, said reset means being controlled by the pulse output of the preceding output terminal.
Claim 3
Dependent Claim
42 words
A signal translating circuit according to claim 1, wherein the gate of the transmission gate transistor is connected to the drain of the source follower transistor, whereby said transmission gate transistor is controlled by one of said first and second clock signals.
Claim 4
Dependent Claim
26 words
A signal translating circuit according to claim 1, wherein said capacitor is a parasitic capacitor formed between the source and gate of said source follower transistor.
Claim 5
Dependent Claim
45 words
A signal translating circuit according to claim 2, further comprising a gate transistor in each stage connected between the source of said source follower transistor and the output terminal, said gate transistor being controlled by the signal at the gate of said source follower transistor.
Claim 6
Dependent Claim
37 words
A signal translating circuit according to claim 1, wherein in each stage the gate of said transmission gate transistor is connected to its drain and thereby said transmission gate transistor is operated as a unidirectional conducting device.