Electron-beam lithographic apparatus

Claim 2

An electron-beam lithographic apparatus comprising: means for generating address data corresponding to a plurality of partial patterns in parallel; pattern memory means specified in parallel by the address data from said address data generating means for forming bit patterns corresponding to said partial patterns in parallel; means for synchronously reading out in parallel said bit patterns from said memory means; means for synthesizing said bit patterns read out in parallel by said reading means to produce a resultant bit pattern in the form of bit data; and means for effecting blanking of an electron beam according to the bit data from said synthesizing means to thereby draw a pattern on an object; wherein said pattern memory means is constituted by a plurality of pair memories, and one bit pattern is formed in one memory in each of said pair memories while previously written bit pattern is being read out from the other memory in each of said pair memories.

Claim 3

An electron-beam lithographic apparatus according to claim 1, wherein said address data generating means includes coordinate data memory means in which coordinate data of partial patterns of a pattern to be drawn are stored, and data converting means for being supplied with coordinate data of said coordinate memory means for one partial pattern and converting said coordinate data into the respective address data.

Claim 4

The electron-beam lithographic apparatus according to claim 1, wherein said synthesizing means is constituted by an OR gate for being supplied with bit patterns from said reading means.

Claim 5

The electron-beam lithographic apparatus according to claim 1, wherein said synthesizing means includes an OR gate for being supplied with the bit patterns from said reading means and an AND gate for being supplied with an output bit pattern from said OR gate and at least one fixed bit pattern.

Claim 6

The electron-beam lithographic apparatus according to claim 1, wherein said synthesizing means includes an OR gate for being supplied with the bit patterns from said reading means and an exclusive OR gate for being supplied with an output bit pattern from said OR gate and at least one fixed bit pattern.

Claim 7

The electron-beam lithographic apparatus according to claim 1, which further comprises means for generating a fixed bit pattern and means for repeatedly supplying the fixed bit pattern from said fixed bit pattern generating means to said synthesizing means.

Claim 8

An electron-beam lithographic apparatus, comprising: a main memory for storing a plurality of partial patterns; a data distributor connected to said memory for distributing said partial patterns from said memory; a plurality of parallel data converters for receiving said partial patterns from said data distributor; a plurality of pairs of parallel pattern memories, each of said pairs being connected to a corresponding one of said data converters; a plurality of pattern data readers, each of said readers being connected to a corresponding pair of pattern memories for receiving a partial pattern therefrom; a first pattern memory of each pair being connected to a data converter while a second pattern memory of each pair is connected to said data reader, said pattern memories alternating connections so that each pattern memory alternately receives and stores a partial pattern from said data converter and reads out said partial pattern to said data reader; a logic gate circuit for receiving a plurality of partial patterns from said plurality of data readers logically combining said partial patterns to form a complete pattern; a blanking circuit connected to said logic gate circuit for blanking an electron beam according to said complete pattern.

Claim 9

An electron-beam lithographic apparatus, comprising: a main memory for storing a plurality of partial patterns; a data distributor connected to said memory for distributing said partial patterns from said memory; a plurality of parallel data converters for receiving said partial patterns from said data distributor; a plurality of pairs of parallel pattern memories, each of said pairs being connected to a corresponding one of said data converters; a plurality of pattern data readers, each of said readers being connected to a corresponding pair of pattern memories for receiving a partial pattern therefrom; a first pattern memory of each pair being connected to a data converter while a second pattern memory of each pair is connected to said data reader, said pattern memories alternating connections so that each pattern memory alternately receives and stores a partial pattern from said data converter and reads out said partial pattern to said data reader; a logic gate circuit for receiving a plurality of partial patterns from said plurality of data readers logically combining said partial patterns to form a complete pattern; a blanking circuit connected to said logic gate circuit for blanking an electron beam according to said complete pattern.