Method of and apparatus for controlling the display of video signal information

Claim 1

A method of displaying video signal information from the external microcomputer or other control system on LCD or other similar display devices, comprising the steps of: supplying output video signals from the external microcomputer to input section including video interface means and display control means; separating said output video signal through said video interface means into signal components including HSYNC, VSYNC, video data and data clock signals which are to be fed into said display control means; storing count control data from a central processor (CPU) connected to said display control means through CPU control bus; counting the number of occurrences of HSYNC and VSYNC signals until the number to be determined by said count control data, and then generating and providing the respective horizontal and vertical addresses to a video buffer memory; counting the number of dot clock signals until the number to be determined by said count control data is reached, and then generating and providing a write pulse to said video buffer memory; converting serial bit video data to parallel bit video data in accordance with the dot clock signals through a delay circuit means and providing said parallel video data to latch circuit means under control of clock signals; transferring said video data to the video buffer memory and storing the same at the horizontal and vertical addresses therein in response to the write pulse; and retrieving any desired portion of the video data from said video buffer memory and transferring it to the LCD display device through LCD buffer RAM.

Claim 2

A method of displaying video signal information from the external microcomputer or other control system on LCD or other similar display devices, comprising the steps of: supplying output video signals from the external microcomputer to input section including video interface means and display control means; separating said output video signal through said video interface means into signal components including HSYNC, VSYNC, video data and data clock signals which are to be fed into said display control means; storing count control data from a central processor (CPU) connected to said display control means through CPU control bus; counting the number of occurrences of HSYNC and VSYNC signals until the number to be determined by said count control data, and then generating and providing the respective horizontal and vertical addresses to a video buffer memory; counting the number of dot clock signals until the number to be determined by said count control data is reached, and then generating and providing a write pulse to said video buffer memory; converting serial bit video data to parallel bit video data in accordance with the dot clock signals through a delay circuit means and providing said parallel video data to latch circuit means under control of clock signals; transferring said video data to the video buffer memory and storing the same at the horizontal and vertical addresses therein in response to the write pulse; and retrieving any desired portion of the video data from said video buffer memory and transferring it to the LCD display device through LCD buffer RAM.

Claim 5

An apparatus for displaying video signal information from the external microcomputer or other control system on LCD or other similar display devices, comprising: input section including video interface means, display control means, and video buffer memory, to which composite video signals from the external microcomputer are to be applied, said interface means including a first block consisting of input buffer for storing data clock signals and a second block consisting of series-connected amplifier and comparator combination which provides separate signal components including HSYNC, VSYNC and video data signals in response to input composite video signal, and said display control means connected to the output of said interface means containing a group of registers each holding the respective control data from a later-defined central processor section and a group of counters each controlled by the corresponding register; central processor section including a central processor (CPU), a read-only memory (ROM), a random access memory (RAM) and keyboard interface all connected through a common CPU bus to the display control means and video buffer memory in said input section, said ROM containing microcoded instructions which enable the central processor to transfer the signal components between the control means and video buffer memory and between the video buffer memory and a later defined display section; and display section connected through said common CPU bus to said input section and to said central processor section, including LCD buffer RAM, LCD interface and display driver.

Claim 6

An apparatus for displaying video signal information from the external microcomputer or other control system on LCD or other similar display devices, comprising: input section including video interface means, display control means, and video buffer memory, to which composite video signals from the external microcomputer are to be applied, said interface means including a first block consisting of input buffer for storing data clock signals and a second block consisting of series-connected amplifier and comparator combination which provides separate signal components including HSYNC, VSYNC and video data signals in response to input composite video signal, and said display control means connected to the output of said interface means containing a group of registers each holding the respective control data from a later-defined central processor section and a group of counters each controlled by the corresponding register; central processor section including a central processor (CPU), a read-only memory (ROM), a random access memory (RAM) and keyboard interface all connected through a common CPU bus to the display control means and video buffer memory in said input section, said ROM containing microcoded instructions which enable the central processor to transfer the signal components between the control means and video buffer memory and between the video buffer memory and a later defined display section; and display section connected through said common CPU bus to said input section and to said central processor section, including LCD buffer RAM, LCD interface and display driver.