Method of encoding a stream of data bits, device for carring out the method, and device for decoding a stream of data bits

Claim 1

A method of encoding a stream of data bits of a binary source signal into a stream of data bits of a binary channel signal in a transmission system, comprising the steps of dividing the bit stream of the source signal into a contiguous sequence of a limited number of permissible source words of variable length wherein the permissible source words are specified in the following table; converting said source words into corresponding channel words, each data bit of a source word resulting in two channel bits of the channel word, wherein said channel words are also specified in said table, and utilizing the following table in said translation: ______________________________________ Source Word Channel Word ______________________________________ W.sub.1 0 00 1 0 0 1 0 0 W.sub.2 0 0(1) 0 0 0 0 W.sub.3 0(1) 0 0 W.sub.4 10 0 1 0 0 W.sub.5 11 1 0 0 0. ______________________________________

Claim 2

A method of encoding a stream of data bits of a binary source signal into a stream of data bits of a binary channel signal in a transmission system, comprising the steps of dividing the bit stream of the source signal into a contiguous sequence of a limited number of permissible source words of variable length wherein the permissible source words are specified in the following table; converting said source words into corresponding channel words, each data bit of a source word resulting in two channel bits of the channel word, wherein said channel words are also specified in said table, and utilizing the following table in said translation: ______________________________________ Source Word Channel Word ______________________________________ W.sub.1 0 00 1 0 0 1 0 0 W.sub.2 0 0(1) 0 0 0 0 W.sub.3 0(1) 0 0 W.sub.4 10 0 1 0 0 W.sub.5 11 1 0 0 0. ______________________________________

Claim 3

A device for encoding a stream of data bits of a binary source signal into a stream of data bits of a binary channel signal in a transmission system wherein the bit stream of the source signal is divided into a contiguous segment of a limited number of permissible source words of variable length, which device converts said permissible source words into corresponding channel words wherein each data bit of a source word results in two channel bits of a channel word and wherein the permissible source words and the corresponding channel words are defined in the following table: ______________________________________ Source Word Channel Word ______________________________________ W.sub.1 0 00 1 0 0 1 0 0 W.sub.2 0 0(1) 0 0 0 0 W.sub.3 0(1) 0 0 W.sub.4 10 0 1 0 0 W.sub.5 11 1 0 0 0 ______________________________________ characterized in that said device comprises: a first shift register for receiving and shifting the data bits of the source signal with a first clock frequency; a second shift register for receiving and shifting the channel bits of the channel signal with a second clock frequency equal to twice the first clock frequency; and a logic circuit for converting the permissible source words into the corresponding channel words which logic circuit comprises three inputs which are connected to three consecutive cells X 1 , X 2 , X 3 of the first shift register, two inputs which are connected to a first and a second cell Y 1 , Y 2 of the second shift register, and two outputs which are connected to a third and a fourth cell Y 3 , Y 4 of the second shift register, which logic circuit is adapted to supply two logic values y 3 and y 4 respectively to the third and the fourth cell Y 3 , Y 4 respectively of the second shift register in accordance with the following algorithm: Y.sub.3 =Y.sub.1 Y.sub.2 x.sub.1 x.sub.2 x.sub.3 +x.sub.1 x.sub.2 Y.sub.4 =x.sub.2 x.sub.1 y.sub.1 +y.sub.1 y.sub.2 x.sub.1 where x 1 , x 2 , x 3 , y 1 , y 2 are the logic values of the respective data and channel bits present in the relevant shift-register cells X 1 , X 2 , X 3 , Y 1 , Y 2 .

Claim 4

A device for encoding a stream of data bits of a binary source signal into a stream of data bits of a binary channel signal in a transmission system wherein the bit stream of the source signal is divided into a contiguous segment of a limited number of permissible source words of variable length, which device converts said permissible source words into corresponding channel words wherein each data bit of a source word results in two channel bits of a channel word and wherein the permissible source words and the corresponding channel words are defined in the following table: ______________________________________ Source Word Channel Word ______________________________________ W.sub.1 0 00 1 0 0 1 0 0 W.sub.2 0 0(1) 0 0 0 0 W.sub.3 0(1) 0 0 W.sub.4 10 0 1 0 0 W.sub.5 11 1 0 0 0 ______________________________________ characterized in that said device comprises: a first shift register for receiving and shifting the data bits of the source signal with a first clock frequency; a second shift register for receiving and shifting the channel bits of the channel signal with a second clock frequency equal to twice the first clock frequency; and a logic circuit for converting the permissible source words into the corresponding channel words which logic circuit comprises three inputs which are connected to three consecutive cells X 1 , X 2 , X 3 of the first shift register, two inputs which are connected to a first and a second cell Y 1 , Y 2 of the second shift register, and two outputs which are connected to a third and a fourth cell Y 3 , Y 4 of the second shift register, which logic circuit is adapted to supply two logic values y 3 and y 4 respectively to the third and the fourth cell Y 3 , Y 4 respectively of the second shift register in accordance with the following algorithm: Y.sub.3 =Y.sub.1 Y.sub.2 x.sub.1 x.sub.2 x.sub.3 +x.sub.1 x.sub.2 Y.sub.4 =x.sub.2 x.sub.1 y.sub.1 +y.sub.1 y.sub.2 x.sub.1 where x 1 , x 2 , x 3 , y 1 , y 2 are the logic values of the respective data and channel bits present in the relevant shift-register cells X 1 , X 2 , X 3 , Y 1 , Y 2 .

Claim 5

A device for decoding a channel signal wherein said channel signal has been obtained by dividing the bit stream of a source signal into a contiguous sequence of a limited number of permissible source words of variable length which have been converted into corresponding channel words, each data bit of a source word resulting in two channel bits of the channel word and wherein said conversion has been effected in accordance with the following table: ______________________________________ Source Word Channel Word ______________________________________ W.sub.1 0 00 1 0 0 1 0 0 W.sub.2 0 0(1) 0 0 0 0 W.sub.3 0(1) 0 0 W.sub.4 10 0 1 0 0 W.sub.5 11 1 0 0 0 ______________________________________ characterized in that the device comprises: a shift register for receiving consecutive channel bits with the clock frequency of the channel signal and a logic circuit having six inputs which are connected to six cells Z 1 to Z 6 of the first shift register for receiving the logic values of six consecutive channel bits of the channel signal, and an output for supplying the source signal, the logic circuit being adapted to supply a logic value W on its output in accordance with the following algorithm: W=y.sub.1 y.sub.4 +y.sub.1 y.sub.4 +y.sub.3 y.sub.6 where y 1 to y 6 are the logic values of the channel bits in the relevant cells Z 1 to Z 6 of the shift register.

Claim 6

A device for decoding a channel signal wherein said channel signal has been obtained by dividing the bit stream of a source signal into a contiguous sequence of a limited number of permissible source words of variable length which have been converted into corresponding channel words, each data bit of a source word resulting in two channel bits of the channel word and wherein said conversion has been effected in accordance with the following table: ______________________________________ Source Word Channel Word ______________________________________ W.sub.1 0 00 1 0 0 1 0 0 W.sub.2 0 0(1) 0 0 0 0 W.sub.3 0(1) 0 0 W.sub.4 10 0 1 0 0 W.sub.5 11 1 0 0 0 ______________________________________ characterized in that the device comprises: a shift register for receiving consecutive channel bits with the clock frequency of the channel signal and a logic circuit having six inputs which are connected to six cells Z 1 to Z 6 of the first shift register for receiving the logic values of six consecutive channel bits of the channel signal, and an output for supplying the source signal, the logic circuit being adapted to supply a logic value W on its output in accordance with the following algorithm: W=y.sub.1 y.sub.4 +y.sub.1 y.sub.4 +y.sub.3 y.sub.6 where y 1 to y 6 are the logic values of the channel bits in the relevant cells Z 1 to Z 6 of the shift register.