Abstract An algorithm and the hardware embodiment for producing a run length limited code useful in magnetic recording channels are described. The system described produces sequences which have a minimum of 1 zero and a maximum of 7 zeros between adjacent 1's. The code is generated by a sequential scheme that map 2 bits of unconstrained into 3 bits of constrained data. The encoder is a finite state machine whose internal state description requires 3 bits. It possesses the attractive feature of reset data blocks which reset it to a fixed state. The decoder requires a lookahead of two future channel symbols (6 bits) and its operation is channel state independent. The error propagation due to a random error is 5 bits. The hardware implementation is extremely simple and can operate at very high data speeds.
An encoder for producing a run length limited (RLL) code for use in a structurally constrained environment having a minimum of 1 and a maximum of seven 0's between adjacent 1's and a coding rate 2/3, said encoder comprising means for receiving as an input vector for a given encoding operation two new message bits (S) and a three bit state vector (X) derived from the immediately preceding encoding operation, logic circuit means for producing a channel vector (Y') obeying said RLL coding rules and a next state vector (X') which becomes the state vector (X) for use in the next encoding operation wherein the vectors Y' and X' are functions of all five input bits to the encoder logic circuit means.
Claim 2
Dependent Claim
122 words
An encoder for producing a run length limited (RLL) code for use in a structurally constrained environment having a minimum of 1 and a maximum of seven 0's between adjacent 1's and a coding rate 2/3, said encoder comprising means for receiving as an input vector for a given encoding operation two new message bits (S) and a three bit state vector (X) derived from the immediately preceding encoding operation, logic circuit means for producing a channel vector (Y') obeying said RLL coding rules and a next state vector (X') which becomes the state vector (X) for use in the next encoding operation wherein the vectors Y' and X' are functions of all five input bits to the encoder logic circuit means.
Claim 3
Dependent Claim
21 words
An encoder as set forth in claim 1 wherein said logic circuit means comprises a maximum of two functional logic levels.
Claim 4
Dependent Claim
56 words
An encoder as set forth in claim 2 wherein said logic circuit means performs a mapping function to map the two input vectors S and X into the two output vectors Y' and X' according to the mapping function table: ______________________________________
##STR3##
##STR4##
LEGEND:
##STR5##
INPUT: S=s1s0,s1=MSB
STATE: X=x2x1x0,x2=MSB
NEXT STATE: X'=x2'x1'x0',x2'=MSB
NEXT OUTPUT: Y'=y2'y1'y0',y2'=MSB
______________________________________