Circuit for generating a deflection current through the field deflection coil of a picture display device

Claim 2

In a circuit for generating a deflection current through the field deflection coil of a picture display device, comprising an amplifier and a sawtooth generator for supplying a sawtooth-shaped signal to the amplifier, said amplifier having an output terminal to which a series arrangement of the deflection coil and a separating capacitor is coupled, and further comprising a feedback network included in a feedback path arranged between the said series arrangement and a feedback input terminal of the amplifier, and also means for deriving from the sawtooth-shaped signal a parabolic signal for application to a signal input terminal of the amplifier, the improvement wherein the means for generating a parabolic signal comprises a multiplying circuit and the feedback path also comprises a combining stage having a first input terminal connected to the sawtooth generator and a second input terminal connected to the feedback network, said combining stage being adapted to apply first and second signals to the multiplying circuit and a third signal to the feedbck input terminal of the amplifier; the first, second and third signals being derived by the combining stage by linear combinations of fractional proporations of the signals at the first and second input terminals thereof, and an output terminal of the multiplying circuit being coupled to the signal input terminal of the amplifier for applying the parabolic signal thereto.

Claim 3

A circuit as claimed in claim 1 wherein the combining stage comprises first and second transistors whose emitters are connected to a first and to a second current source, respectively, and interconnected by a resistance network, the base of the first transistor being connected to the first input terminal and the base of the second transistor to the second input terminal of the combining stage, the current through the resistance network producing the first signal and the voltages at the collectors of said transistors producing the second signal for application to the multiplying circuit.

Claim 4

A circuit as claimed in claim 2 wherein the multiplying circuit is of symmetrical configuration and the voltage across a resistor of the resistance network constitutes the first signal and the differential voltage between the collector of the first transistor and the collector of the second transistor constitutes the second signal for application to the multiplying circuit.

Claim 5

A circuit as claimed in claim 3 wherein the multiplying circuit comprises a first and a second differential amplifier, each differential amplifier comprising a first and a second transistor having interconnected emitters, the interconnected emitters of the transistors of said first and second differential amplifiers being respectively connected to the collectors of third and fourth transistors, said third and fourth transistors forming a third differential amplifier in which the emitters thereof are interconnected and the bases thereof are respectively connected to the collectors of the first and second transistors of the combining stage, the base of the first transistor of the first differential amplifier being connected to the base of the second transistor of the second differential amplifier and to a terminal of the said resistor of the resistance network, while the base of the second transistor of the first differential amplifier is connected to the base of the first transistor of the second differential amplifier and to the other terminal of the resistor, the collector of the first transistor of the first differential amplifier being connected to the first transistor of the second differential amplifier and the collector of the second transistor of the first differential amplifier being connected to the collector of the second transistor of the second differential amplifier, the connections thus formed being symmetrical and one of such connections forming the output terminal of the multiplying circuit.

Claim 6

A circuit as claimed in claim 1, wherein the output terminal of the multiplying circuit is connected to a tap of a voltage divider which determines the d.c. voltage setting at the signal input terminal of the amplifier.

Claim 7

A circuit as claimed in claim 2, wherein the voltage at a point of the resistance network is the third signal generated by the combining stage, the said point being connected to the feedback input terminal of the amplifier.

Claim 8

A circuit as claimed in claim 1 further comprising a second amplifier for producing a deflection current having a field frequency which deviates from the field frequency of the deflection current produced by the first mentioned amplifier and having a substantially equal amplitude, the combining stage applying a fourth signal different from the third signal to a feedback input terminal of the second amplifier which fourth signal is a linear combination of fractional proportions of the signals at the first and the second input terminals of the combining stage, the output terminal of the multiplying circuit being coupled to a signal input terminal of the second amplifier and the output terminal of the first amplifier and the output terminal of the second amplifier being coupled to the series arrangement of the deflection coil and the separating capacitor via an adder stage.

Claim 9

A circuit as claimed in claim 3 wherein the linearity of the second signal applied to the multiplying circuit by the combining stage is corrected and the linearity of the first signal applied to the multiplying circuit by the combining stage is not corrected.

Claim 10

A circuit as claimed in claim 7 further comprising a resistor connected in series with a current source, one terminal of the resistor being connected to the signal input terminal of the first amplifier and the other terminal of the resistor being connected to the signal input terminal of the second amplifier for co-determining the d.c. voltage settings of both amplifiers.

Claim 11

A circuit as claimed in claim 1 wherein the output terminal of the multiplying circuit is connected to a circuit for correcting the operation of the picture display device.