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US4535295A Expired / Lapsed US ⏱️ 0.0 years remaining

Method and device for controlling the phase of timing signal

Assignee: Hitachi Ltd
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Filing: 1982-11-24
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Granted: 1985-08-13
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Expires: 2002-11-24
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Abstract

Abstract Disclosed is a phase control system for providing by digital processing a timing signal having a certain phase relationship with a timing signal detected in a received, modulated signal, wherein the detected timing signal is delayed by a predetermined time period and the detected timing signal and the delayed timing signal are multiplied by respective constants so that the zero-cross point of the composite signal of the two timing signals matches the sampling point of the timing signal.

Inventors

  • 👤 Yoshiro Kokuryo

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 14:45
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0079; H04L7/0087; G; G01; G01R; G01R19/00; G01R19/175; H03; H03K; H03K5/00; H03K5/153; H03K5/1536; H04L7/02; H04L7/033; H04L7/0337

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 127 words
A timing signal pulse control circuit comprising timing signal component detecting means for extracting a timing signal component from a received signal, a sampling circuit which samples said timing signal component in response to the output pulses of a digital signal generator, means including a phase shift circuit for shifting the phase of the output signal from said sampling circuit, detection means for detecting the zero-cross point of the phase-shifted signal produced by said phase shift circuit, and control for controlling the phase of the output of said digital signal generator in response to the output of said detection means so that the output pulses of said digital signal generator are produced at the zero-cross points of the phase shifted signal produced by said phase shift circuit.
Claim 2
Dependent Claim 127 words
A timing signal pulse control circuit comprising timing signal component detecting means for extracting a timing signal component from a received signal, a sampling circuit which samples said timing signal component in response to the output pulses of a digital signal generator, means including a phase shift circuit for shifting the phase of the output signal from said sampling circuit, detection means for detecting the zero-cross point of the phase-shifted signal produced by said phase shift circuit, and control for controlling the phase of the output of said digital signal generator in response to the output of said detection means so that the output pulses of said digital signal generator are produced at the zero-cross points of the phase shifted signal produced by said phase shift circuit.
Claim 3
Dependent Claim 85 words
A timing signal phase control circuit according to claim 1, wherein said phase shift circuit comprises first multiplying means for multiplying the output signal of said sampling circuit by a first constant, delay means for delaying the output signal of said sampling circuit by a multiple of a sampling period, second multiplying means for multiplying the output of said delay means by a second constant, and adding means for adding the outputs of said first and second multiplying means to produce said phase shifted signal.
Claim 4
Independent Claim 137 words
A method of controlling the phase of a timing pulse signal in a signal processing system by extracting a timing signal component from a received signal and providing a certain phase difference between the timing pulse signal and a zero-cross point of said timing signal component, comprising: (a) multiplying a sampled signal of said timing signal component by a first constant; (b) delaying said sampled signal by a multiple of the sampling period at which said sampled signal is obtained from said timing signal component; (c) multiplying said delayed sampled signal by a second constant; (d) adding the two signals obtained by steps (a) and (c) in order to obtain a phase shifted timing signal; and (e) producing said timing pulse signal having a pulse which coincides with the zero-cross point of said phase shifted timing signal.
Claim 5
Independent Claim 137 words
A method of controlling the phase of a timing pulse signal in a signal processing system by extracting a timing signal component from a received signal and providing a certain phase difference between the timing pulse signal and a zero-cross point of said timing signal component, comprising: (a) multiplying a sampled signal of said timing signal component by a first constant; (b) delaying said sampled signal by a multiple of the sampling period at which said sampled signal is obtained from said timing signal component; (c) multiplying said delayed sampled signal by a second constant; (d) adding the two signals obtained by steps (a) and (c) in order to obtain a phase shifted timing signal; and (e) producing said timing pulse signal having a pulse which coincides with the zero-cross point of said phase shifted timing signal.
Claim 6
Dependent Claim 151 words
A timing signal control circuit comprising: (a) digital signal generator means for providing timing pulses to be used for sampling and signal processing; (b) sampling means for sampling a received signal in response to said timing pulses; (c) means including a timing signal component detecting circuit connected to said sampling means for extracting a timing signal component from the output of said sampling means; (d) phase shift means connected to said timing signal component detecting circuit for shifting the phase of said timing signal component; (e) detection means for detecting the zero-cross point of the phase-shifted timing signal component produced by said phase shift means; and (f) control means for controlling the digital signal generator means in response to the output of said detection means so that the phase of the timing pulses produced by said digital signal generator means coincides with the zero-cross point of the phase-shifted timing signal component.
Claim 7
Dependent Claim 151 words
A timing signal control circuit comprising: (a) digital signal generator means for providing timing pulses to be used for sampling and signal processing; (b) sampling means for sampling a received signal in response to said timing pulses; (c) means including a timing signal component detecting circuit connected to said sampling means for extracting a timing signal component from the output of said sampling means; (d) phase shift means connected to said timing signal component detecting circuit for shifting the phase of said timing signal component; (e) detection means for detecting the zero-cross point of the phase-shifted timing signal component produced by said phase shift means; and (f) control means for controlling the digital signal generator means in response to the output of said detection means so that the phase of the timing pulses produced by said digital signal generator means coincides with the zero-cross point of the phase-shifted timing signal component.
Claim 8
Dependent Claim 91 words
A timing signal phase control circuit according to claim 4, wherein said phase shift means comprises: first multiplying means for multiplying the output of said timing signal component detecting circuit by a first constant; delay means for delaying the output signal of said timing signal component detecting circuit by a multiple of a sampling period; second multiplying means for multiplying the output of said delay means by a second constant; and adding means for adding the outputs of said first and second multiplying means in order to obtain said phase-shifted signal.
Claim 9
Dependent Claim 24 words
A timing signal phase control circuit according to claim 5, wherein at least one of said first and second constants is equal to one.
Claim 10
Dependent Claim 106 words
A timing signal phase control circuit according to claim 4, wherein said detection means comprises a polarity discrimination circuit which discriminates the polarity of the output of said phase shift means at a sampling interval, and said control means for controlling said digital signal generator means comprises quantization means for transforming the output of said polarity discrimination circuit into a bilevel signal, means including a loop filter for filtering the output of said quantization means, and means including a pulse adding/eliminating circuit which adds or eliminates a pulse to/from output pulses from said digital signal generator means in response to the output of said loop filter.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1988-08-12 1989-02-11 1989-08-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1992-08-12 1993-02-11 1993-08-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1996-08-12 1997-02-11 1997-08-13 $7700.00 Window Closed / Lapsed

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