Clock synchronizer and data detector

Claim 2

In a system adapted to receive a stream of data having specific switching points defining the data, a clock synchronizer and data detector comprising: (a) a source of clock pulses having first and second outputs with first and second reference signals available at the outputs, respectively, said reference signals being separated in phase by a predetermined number of electrical degrees; (b) first multiplying means connected to multiply the received stream of data by each of the first and second reference signals and provide first and second products; (c) low pass filter means connected to receive the two products from said first multiplying means and substantially reduce the noise content therein; (d) second multiplying means connected to receive the filtered first and second products from said filter means and the first and second reference signals from said clock source for multiplying the first product by the second reference signal and the second product by the first reference signal and providing a pair of products; (e) combining means connected to receive the pair of products from said second multiplying means for combining the products into a single stream of clock pulses having a predetermined phase relationship with respect to the switching points of the stream of data; and (f) sampling means connected to receive the stream of data and the stream of clock pulses from said combining means for sampling the data approximately at each of the switching points in response to the stream of clock pulses.

Claim 3

A clock synchronizer and data detector as claimed in claim 1 wherein the sampling means includes a clocked flip-flop.

Claim 4

In a system adapted to receive data generally in the form of a stream of pulses having specific switching points defining the data, a clock synchronizer and data detector comprising: (a) a source of clock pulses having first and second outputs with first and second reference signals available at the outputs, respectively, said reference signals having a 90° electrical phase separation; (b) a first pair of multipliers connected to multiply the received stream of pulses by each of the first and second reference signals and provide first and second products; (c) low pass filter means connected to receive the two products from said first pair of multipliers and substantially reduce the noise content therein; (d) a second pair of multipliers connected to receive the filtered first and second products from said filter means and the first and second reference signals from said clock source for multiplying the first product by the second reference signal and the second product by the first reference signal and providing a pair of products at outputs thereof; (e) combining means connected to receive the pair of products from said second pair of multipliers for combining the products into a single stream of clock pulses in-phase with the switching points of the data received; and (f) sampling means connected to receive the stream of data and the stream of clock pulses from said combining means for sampling the data at each of the switching points in response to the stream of clock pulses.

Claim 5

In a system adapted to receive data generally in the form of a stream of pulses having specific switching points defining the data, a clock synchronizer and data detector comprising: (a) a source of clock pulses having first and second outputs with first and second reference signals available at the outputs, respectively, said reference signals having a 90° electrical phase separation; (b) a first pair of multipliers connected to multiply the received stream of pulses by each of the first and second reference signals and provide first and second products; (c) low pass filter means connected to receive the two products from said first pair of multipliers and substantially reduce the noise content therein; (d) a second pair of multipliers connected to receive the filtered first and second products from said filter means and the first and second reference signals from said clock source for multiplying the first product by the second reference signal and the second product by the first reference signal and providing a pair of products at outputs thereof; (e) combining means connected to receive the pair of products from said second pair of multipliers for combining the products into a single stream of clock pulses in-phase with the switching points of the data received; and (f) sampling means connected to receive the stream of data and the stream of clock pulses from said combining means for sampling the data at each of the switching points in response to the stream of clock pulses.

Claim 6

In a system adapted to receive a stream of data having specific switching points defining the data, a clock synchronizer and data detector comprising: (a) input means connected to receive the stream of data for converting the data to an output signal having unidirectional pulses; (b) a source of clock pulses having first and second outputs with first and second reference signals available at the outputs, respectively, said reference signal having a 90° electrical phase separation; (c) a first pair of multipliers connected to multiply the output signal from said input means by each of the first and second reference signals and provide first and second products at two outputs; (d) low pass filter means connected to receive the two products from said first pair of multipliers and substantially reduce the noise content therein; (e) a second pair of multipliers connected to receive the filtered first and second products from said filter means and the first and second reference signals from said clock source for multiplying the first product by the second reference signal and the second product by the first reference signal and providing a pair of products at outputs thereof; (f) combining means connected to receive the pair of products from said second pair of multipliers for combining the products into a single stream of clock pulses in-phase with the switching points of the data received; and (g) sampling means connected to receive the stream of data and the stream of clock pulses from said combining means for sampling the data at each of the switching points in response to the stream of clock pulses.

Claim 7

In a system adapted to receive a stream of data having specific switching points defining the data, a clock synchronizer and data detector comprising: (a) input means connected to receive the stream of data for converting the data to an output signal having unidirectional pulses; (b) a source of clock pulses having first and second outputs with first and second reference signals available at the outputs, respectively, said reference signal having a 90° electrical phase separation; (c) a first pair of multipliers connected to multiply the output signal from said input means by each of the first and second reference signals and provide first and second products at two outputs; (d) low pass filter means connected to receive the two products from said first pair of multipliers and substantially reduce the noise content therein; (e) a second pair of multipliers connected to receive the filtered first and second products from said filter means and the first and second reference signals from said clock source for multiplying the first product by the second reference signal and the second product by the first reference signal and providing a pair of products at outputs thereof; (f) combining means connected to receive the pair of products from said second pair of multipliers for combining the products into a single stream of clock pulses in-phase with the switching points of the data received; and (g) sampling means connected to receive the stream of data and the stream of clock pulses from said combining means for sampling the data at each of the switching points in response to the stream of clock pulses.

Claim 8

A clock synchronizer and data detector as claimed in claim 4 wherein the input means includes an absolute value determining circuit.

Claim 9

A clock synchronizer and data detector as claimed in claim 5 wherein the absolute value determining circuit includes a square law detector.

Claim 10

A clock synchronizer and data detector as claimed in claim 4 wherein the sampling means includes a clocked flip-flop.

Claim 13

A method according to claim 8 wherein the streams of clock pulses are separated in phase by ninety electrical degrees.

Claim 14

A method according to claim 8 wherein the sampling is performed during the clock pulses and approximately at the switching points of the stream of data.