Device structures for high density integrated circuits

Claim 2

A semiconductor device comprising: an insulating substrate, a semiconductor layer having an upper and lower surface positioned on said insulating substrate and having a predetermined thickness, first and second spaced-apart edges formed by sidewall surfaces extending between said upper and lower surface of said semiconductor layer, said semiconductor layer doped with impurities to exhibit a first type material, said first and second edges doped with impurities of a second type introduced through said sidewall surfaces to a predetermined depth from said respective edge to form first and second regions of a second type, a layer of insulation positioned over said upper surface of said semiconductor layer extending between said first and second regions, a layer of conductive material positioned over said insulation layer and extending between said first and second regions, first means for making ohmic contact to said first region including aluminum deposited on said first region and extending over onto said upper surface of said semiconductor layer, and second means for making ohmic contact to said second region.

Claim 3

The semiconductor device of claim 1 wherein said semiconductor layer is n type and said aluminum in contact with said semiconductor layer forms a Schottky barrier dode.

Claim 4

A semiconductor device comprising: an insulating substrate, a semiconductor layer having an upper and lower surface positioned on said insulating substrate and having a predetermined thickness, said semiconductor layer having sidewall surfaces extending between said upper and lower surface of said semiconductor layer, said semiconductor layer doped with impurities to exhibit a first type material, said sidewall doped with impurities of a second type to a predetermined depth from said sidewall in at least two selected areas spaced apart along a common sidewall to form first and second spaced apart regions of a second type separated by a sidewall region of said first type, a layer of insulation positioned over said side wall of said semiconductor layer and extending between said first and second regions, a layer of conductive material positioned over said insulation layer and extending between said first and second regions, and means for making ohmic contact to said first and second regions.

Claim 5

A semiconductor device comprising: an insulating substrate, a semiconductor layer having an upper and lower surface positioned on said insulating substrate and having a predetermined thickness, said semiconductor layer having sidewall surfaces extending between said upper and lower surface of said semiconductor layer, said semiconductor layer doped with impurities to exhibit a first type material, said sidewall doped with impurities of a second type to a predetermined depth from said sidewall in at least two selected areas spaced apart along a common sidewall to form first and second spaced apart regions of a second type separated by a sidewall region of said first type, a layer of insulation positioned over said side wall of said semiconductor layer and extending between said first and second regions, a layer of conductive material positioned over said insulation layer and extending between said first and second regions, and means for making ohmic contact to said first and second regions.

Claim 6

A read only memory array comprising: an insulating substrate having an upper surface, a plurality of spaced apart semiconductor strips having an upper and lower surface and positioned on said upper surface of said substrate, each said strip having a first and second edge on either side of said strip extending from said lower surface to said upper surface, said semiconductor strips doped with impurities to exhibit material of a first type, said first edge of each strip doped with impurities of a second type formed by introducing selected impurities through said first edge to form a first region of a second type extending from said first edge into said semiconductor strip to a depth in the range from 0.1 to 1 micrometer, each said strip having an insulation layer over its upper surface and first and second edges except at predetermined upper surface locations, a plurality of spaced apart aluminum metallization strips extending over and transverse to said plurality of semiconductor strips including said first region and contacting said semiconductor strip at said predetermined upper surface locations.

Claim 7

A read only memory array comprising: an insulating substrate having an upper surface, a plurality of spaced apart semiconductor strips having an upper and lower surface and positioned on said upper surface of said substrate, each said strip having a first and second edge on either side of said strip extending from said lower surface to said upper surface, said semiconductor strips doped with impurities to exhibit material of a first type, said first edge of each strip doped with impurities of a second type formed by introducing selected impurities through said first edge to form a first region of a second type extending from said first edge into said semiconductor strip to a depth in the range from 0.1 to 1 micrometer, each said strip having an insulation layer over its upper surface and first and second edges except at predetermined upper surface locations, a plurality of spaced apart aluminum metallization strips extending over and transverse to said plurality of semiconductor strips including said first region and contacting said semiconductor strip at said predetermined upper surface locations.

Claim 8

A semiconductor device comprising: an insulating substrate, a semiconductor layer having an upper and lower surface positioned on said insulating substrate, first and second spaced-apart sidewall surfaces extending between said upper and lower surface of said semiconductor layer, said semiconductor layer doped with impurities to exhibit a first type material, said semiconductor layer including first and second spaced apart regions of a second type formed by introducing selected impurities through selected areas of said first and second sidewall surfaces respectively, a layer of insulation positioned over said upper surface of said semiconductor layer extending between said first and second regions, a layer of conductive material positioned over said insulation layer and extending between said first and second regions, said semiconductor layer being rectangular in shape and said first region extending beyond a first side of said layer of conductive material along a sidewall to a first corner of said rectangular semiconductor layer, and aluminum deposited over exposed portions of said first region and over exposed portions of said semiconductor layer.

Claim 9

A semiconductor device comprising: an insulating substrate, a semiconductor layer having an upper and lower surface positioned on said insulating substrate, first and second spaced-apart sidewall surfaces extending between said upper and lower surface of said semiconductor layer, said semiconductor layer doped with impurities to exhibit a first type material, said semiconductor layer including first and second spaced apart regions of a second type formed by introducing selected impurities through selected areas of said first and second sidewall surfaces respectively, a layer of insulation positioned over said upper surface of said semiconductor layer extending between said first and second regions, a layer of conductive material positioned over said insulation layer and extending between said first and second regions, said semiconductor layer being rectangular in shape and said first region extending beyond a first side of said layer of conductive material along a sidewall to a first corner of said rectangular semiconductor layer, and aluminum deposited over exposed portions of said first region and over exposed portions of said semiconductor layer.

Claim 10

The semiconductor device of claim 5 wherein said semiconductor layer is n type and said aluminum over exposed portions of said semiconductor layer forms a Schottky barrier diode.

Claim 11

A semiconductor device comprising: an insulating substrate, a semiconductor layer having an upper and lower surface positioned on said insulating substrate, first and second spaced-apart sidewall surfaces extending between said upper and lower surface of said semiconductor layer, said semiconductor layer doped with impurities to exhibit a first type material, said semiconductor layer including first and second spaced apart regions of a second type formed by introducing selected impurities through selected areas of said first and second sidewall surfaces respectively, a layer of insulation positioned over said upper surface of said semiconductor layer extending between said first and second regions, a layer of conductive material positioned over said insulation layer and extending between said first and second regions, and first means for making ohmic contact to said first region including aluminum deposited on said first region and extending over onto said semiconductor layer.

Claim 12

A semiconductor device comprising: an insulating substrate, a semiconductor layer having an upper and lower surface positioned on said insulating substrate, first and second spaced-apart sidewall surfaces extending between said upper and lower surface of said semiconductor layer, said semiconductor layer doped with impurities to exhibit a first type material, said semiconductor layer including first and second spaced apart regions of a second type formed by introducing selected impurities through selected areas of said first and second sidewall surfaces respectively, a layer of insulation positioned over said upper surface of said semiconductor layer extending between said first and second regions, a layer of conductive material positioned over said insulation layer and extending between said first and second regions, and first means for making ohmic contact to said first region including aluminum deposited on said first region and extending over onto said semiconductor layer.

Claim 13

The semiconductor device of claim 7 wherein said semiconductor layer is n type and said aluminum in contact with said semiconductor layer forms a Schottky barrier diode.

Claim 14

A semiconductor device comprising: an insulating substrate, a semiconductor layer having an upper and lower surface positioned on said insulating substrate and having a first sidewall surface extending between said upper and lower surface, said semiconductor layer doped with impurities to exhibit a first type material, said first sidewall including first and second spaced apart regions of a second type, a layer of insulation positioned over said first side wall of said semiconductor layer and extending between said first and second regions, a layer of conductive material positioned over said insulation layer and extending between said first and second regions, and first means for making ohmic contact to said first region including aluminum deposited over said first region and over said semiconductor layer, and wherein said semiconductor layer is n type and said aluminum over said semiconductor layer forms a Schottky barrier diode.

Claim 15

A semiconductor device comprising: an insulating substrate, a semiconductor layer having an upper and lower surface positioned on said insulating substrate and having a first sidewall surface extending between said upper and lower surface, said semiconductor layer doped with impurities to exhibit a first type material, said first sidewall including first and second spaced apart regions of a second type, a layer of insulation positioned over said first side wall of said semiconductor layer and extending between said first and second regions, a layer of conductive material positioned over said insulation layer and extending between said first and second regions, and first means for making ohmic contact to said first region including aluminum deposited over said first region and over said semiconductor layer, and wherein said semiconductor layer is n type and said aluminum over said semiconductor layer forms a Schottky barrier diode.

Claim 16

The semiconductor device of claim 9 wherein said first region extends from said first sidewall surface to a predetermined distance into said semiconductor layer.

Claim 17

The semiconductor device of claim 10 wherein said predetermined distance from said first sidewall surface is in the range from 0.5 to 1 micrometer.

Claim 18

The semiconductor device of claim 10 wherein said predetermined distance from said first sidewall surface is in the range from 1000 to 3000 angstroms.

Claim 19

The semiconductor device of claim 9 wherein said first and second spaced apart regions are formed at times said upper surface of said semiconductor layer if protected by a layer of material impervious to said selected impurities.

Claim 20

The semiconductor device of claim 13 wherein said layer of material includes thermal oxide.

Claim 21

A semiconductor circuit comprising: an insulating substrate having an upper surface, a semiconductor island having an upper and lower surface and positioned on said upper surface of said substrate, said semiconductor island having an edge around said island extending from said lower surface to said upper surface, said semiconductor island doped with impurities to exhibit material of a first type, a first layer of dielectric material covering the upper surface of said semiconductor island, said edge doped to form at least first, second and third edge segments with impurities of a second type formed by introducing selected impurities through said edge, said first and second edge segments spaced apart along an edge by a first predetermined distance, a second layer of dielectric material covering the edge between said first and second segments, said second and third edge segments having portions spaced apart across said semiconductor island, a conductive electrode overlying a path over said first layer of dielectric material between said second and third edge segments and overlying a path over said second layer of dielectric material between said first and second edge segments to couple said first, second and third edge segments together at times a predetermined voltage is applied to said conductive electrode, means for making ohmic contact to said first edge segment including aluminum deposited over said first segment and over said semiconductor island, and wherein said semiconductor island is n type, and said aluminum over said semiconductor layer forms a Schottky barrier diode.

Claim 22

A semiconductor circuit comprising: an insulating substrate having an upper surface, a semiconductor island having an upper and lower surface and positioned on said upper surface of said substrate, said semiconductor island having an edge around said island extending from said lower surface to said upper surface, said semiconductor island doped with impurities to exhibit material of a first type, a first layer of dielectric material covering the upper surface of said semiconductor island, said edge doped to form at least first, second and third edge segments with impurities of a second type formed by introducing selected impurities through said edge, said first and second edge segments spaced apart along an edge by a first predetermined distance, a second layer of dielectric material covering the edge between said first and second segments, said second and third edge segments having portions spaced apart across said semiconductor island, a conductive electrode overlying a path over said first layer of dielectric material between said second and third edge segments and overlying a path over said second layer of dielectric material between said first and second edge segments to couple said first, second and third edge segments together at times a predetermined voltage is applied to said conductive electrode, means for making ohmic contact to said first edge segment including aluminum deposited over said first segment and over said semiconductor island, and wherein said semiconductor island is n type, and said aluminum over said semiconductor layer forms a Schottky barrier diode.

Claim 23

The semiconductor circuit of claim 15 further including means for making ohmic contact to at least two of said first, second and third edge segments.

Claim 24

A semiconductor circuit comprising: an insulating substrate having an upper surface, a semiconductor island having an upper and lower surface and positioned on said upper surface of said substrate, said semiconductor island having an edge around said island extending from said lower surface to said upper surface, said semiconductor island doped with impurities to exhibit material of a first type, a first layer of dielectric material covering the upper surface of said semiconductor island, said edged doped to form at least first, second and third edge segments with impurities of a second type formed by introducing selected impurities through said edge, said first and second edge segments spaced apart along an edge by a first predetermined distance, a second layer of dielectric material covering the edge between said first and second edge segments, said second and third edge segments having portions spaced apart across said semiconductor island, a first conductive electrode overlying a path over said first layer of dielectric material between said second and third edge segments to couple said second and third edge segments together at times a first predetermined voltage is applied to said first conductive electrode, a second conductive electrode overlying a path over said second layer of dielectric material between said first and second edge segments to couple said first and second edge segments together at times a second predetermined voltage is applied to said second conductive electrode, means for making ohmic contact to said first edge segment including aluminum deposited over said first segment and over said semiconductor island, and wherein said semiconductor island is n type, and said aluminum over said semiconductor layer forms a Schottky barrier diode.

Claim 25

A semiconductor circuit comprising: an insulating substrate having an upper surface, a semiconductor island having an upper and lower surface and positioned on said upper surface of said substrate, said semiconductor island having an edge around said island extending from said lower surface to said upper surface, said semiconductor island doped with impurities to exhibit material of a first type, a first layer of dielectric material covering the upper surface of said semiconductor island, said edged doped to form at least first, second and third edge segments with impurities of a second type formed by introducing selected impurities through said edge, said first and second edge segments spaced apart along an edge by a first predetermined distance, a second layer of dielectric material covering the edge between said first and second edge segments, said second and third edge segments having portions spaced apart across said semiconductor island, a first conductive electrode overlying a path over said first layer of dielectric material between said second and third edge segments to couple said second and third edge segments together at times a first predetermined voltage is applied to said first conductive electrode, a second conductive electrode overlying a path over said second layer of dielectric material between said first and second edge segments to couple said first and second edge segments together at times a second predetermined voltage is applied to said second conductive electrode, means for making ohmic contact to said first edge segment including aluminum deposited over said first segment and over said semiconductor island, and wherein said semiconductor island is n type, and said aluminum over said semiconductor layer forms a Schottky barrier diode.

Claim 26

The semiconductor circuit of claim 17 further including means for making ohmic contact to at least two of said first, second and third segments.

Claim 27

The semiconductor circuit of claim 17 wherein said second conductive electrode is in ohmic contact with said first edge segment.

Claim 28

A row decoder circuit comprising: an insulating substrate having an upper surface, a plurality of spaced apart semiconductor strips having an upper and lower surface and positioned on said upper surface of said substrate, each said strip having a first and second edge on either side of said strip extending from said lower surface to said upper surface, said semiconductor strips doped with impurities to exhibit material of a first type, said first and second edges of each strip doped at predetermined edge segments with impurities of a second type formed by introducing selected impurities through said first and second edges at said predetermined edge segments to form a plurality of spaced apart doped edge segments, said doped edge segments extending 0.7 micrometers from said edge into said semiconductor strip, said doped edge segments on said first and second edges having portions positioned opposite one another across a respective semiconductor strip, each strip having an insulation layer over its upper surface and first and second edges, a plurality of spaced apart conductive strips extending over and transverse to said plurality of semiconductor strips and over doped edge segments positioned opposite one another to form MOS transistors, said MOS transistors and doped edge segments interconnected along one semiconductor strip to form a continuous conductive path at times said transistors in said semiconductor strip are conductive and non-conductive at times one or more of said MOS transistors are non-conductive.

Claim 29

A row decoder circuit comprising: an insulating substrate having an upper surface, a plurality of spaced apart semiconductor strips having an upper and lower surface and positioned on said upper surface of said substrate, each said strip having a first and second edge on either side of said strip extending from said lower surface to said upper surface, said semiconductor strips doped with impurities to exhibit material of a first type, said first and second edges of each strip doped at predetermined edge segments with impurities of a second type formed by introducing selected impurities through said first and second edges at said predetermined edge segments to form a plurality of spaced apart doped edge segments, said doped edge segments extending 0.7 micrometers from said edge into said semiconductor strip, said doped edge segments on said first and second edges having portions positioned opposite one another across a respective semiconductor strip, each strip having an insulation layer over its upper surface and first and second edges, a plurality of spaced apart conductive strips extending over and transverse to said plurality of semiconductor strips and over doped edge segments positioned opposite one another to form MOS transistors, said MOS transistors and doped edge segments interconnected along one semiconductor strip to form a continuous conductive path at times said transistors in said semiconductor strip are conductive and non-conductive at times one or more of said MOS transistors are non-conductive.

Claim 30

The row decoder of claim 20 wherein said semiconductor strips are four micrometers wide.

Claim 31

The row decoder of claim 20 wherein said semiconductor strips are spaced four micrometers apart.

Claim 32

The row decoder of claim 20 wherein said material of a first type is n type.

Claim 33

The row decoder of claim 20 wherein said conductive strips are four micrometers wide.

Claim 34

The read only memory of claim 4 wherein said semiconductor strips are four micrometers wide.

Claim 35

The read only memory of claim 4 wherein said semiconductor strips are spaced four micrometers apart.

Claim 36

The read only memory of claim 4 wherein said material of a first type is n type.

Claim 37

The read only memory of claim 4 wherein said aluminum metallization strips are four micrometers wide.

Claim 38

A read only memory array comprising: an insulating substrate having an upper surface, a plurality of spaced apart semiconductor strips having an upper and lower surface and positioned on said upper surface of said substrate, each said strip having a first and second edge on either side of said strip extending from said lower surface to said upper surface, said semiconductor strips doped with impurities to exhibit material of a first type, said first edge of each strip doped with impurities of a second type formed by introducing selected impurities through said first edge to form a first region of a second type extending 0.7 micrometers from said first edge into said semiconductor strip, each said strip having an insulation layer over its upper surface and first and second edges except at predetermined upper surface locations, a plurality of spaced apart aluminum metallization strips extending over and transverse to said plurality of semiconductor strips including said first region and contacting said semiconductor strip at said predetermined upper surface locations.

Claim 39

A read only memory array comprising: an insulating substrate having an upper surface, a plurality of spaced apart semiconductor strips having an upper and lower surface and positioned on said upper surface of said substrate, each said strip having a first and second edge on either side of said strip extending from said lower surface to said upper surface, said semiconductor strips doped with impurities to exhibit material of a first type, said first edge of each strip doped with impurities of a second type formed by introducing selected impurities through said first edge to form a first region of a second type extending 0.7 micrometers from said first edge into said semiconductor strip, each said strip having an insulation layer over its upper surface and first and second edges except at predetermined upper surface locations, a plurality of spaced apart aluminum metallization strips extending over and transverse to said plurality of semiconductor strips including said first region and contacting said semiconductor strip at said predetermined upper surface locations.

Claim 40

The read only memory of claim 4 wherein said first region of each semiconductor strip is coupled through a respective resistor to a first voltage potential.

Claim 41

The read only memory of claim 4 wherein said insulation layer extends a predetermined distance from said first region to said predetermined upper surface location, said upper surface location forms an opening in said insulation layer exposing said upper surface of said semiconductor strip.

Claim 42

A read only memory array comprising: an insulating substrate having an upper surface, a plurality of spaced apart semiconductor strips having an upper and lower surface and positioned on said upper surface of said substrate, each said strip having a first and second edge on either side of said strip extending from said lower surface to said upper surface, said semiconductor strips doped with impurities to exhibit material of a first type, said first edge of each strip doped with impurities of a second type formed by introducing selected impurities through said first edge to form a first region of a second type, each said strip having an insulation layer over its upper surface and first and second edges except at predetermined upper surface locations, a plurality of spaced apart aluminum metallization strips extending over and transverse to said plurality of semiconductor strips including said first region and contacting said semiconductor strip at said predetermined upper surface locations, said insulation layer extending a predetermined distance from said first region to said predetermined upper surface location, said upper surface location forms an opening in said insulation layer exposing said upper surface of said semiconductor strip, and said aluminum metallization strip contacting each predetermined upper surface location forms the gate of a field effect transistor having a drain formed by the aluminum metallization strip in contact with said upper surface location and source formed by said first region.

Claim 43

A read only memory array comprising: an insulating substrate having an upper surface, a plurality of spaced apart semiconductor strips having an upper and lower surface and positioned on said upper surface of said substrate, each said strip having a first and second edge on either side of said strip extending from said lower surface to said upper surface, said semiconductor strips doped with impurities to exhibit material of a first type, said first edge of each strip doped with impurities of a second type formed by introducing selected impurities through said first edge to form a first region of a second type, each said strip having an insulation layer over its upper surface and first and second edges except at predetermined upper surface locations, a plurality of spaced apart aluminum metallization strips extending over and transverse to said plurality of semiconductor strips including said first region and contacting said semiconductor strip at said predetermined upper surface locations, said insulation layer extending a predetermined distance from said first region to said predetermined upper surface location, said upper surface location forms an opening in said insulation layer exposing said upper surface of said semiconductor strip, and said aluminum metallization strip contacting each predetermined upper surface location forms the gate of a field effect transistor having a drain formed by the aluminum metallization strip in contact with said upper surface location and source formed by said first region.

Claim 44

The read only memory of claim 32 wherein said aluminum metallization strip in contact with said predetermined upper surface locations forms a Schottky barrier diode with said semiconductor strip.

Claim 45

The read only memory of claim 32 wherein said first type is N type, said first region of each semiconductor strip is coupled through a respective resistor to a first voltage potential and wherein said aluminum metallization strips are coupled to a row decoder, said row decoder responsive to address signals for selecting one of said metallization strips and coupling a second voltage potential which is negative with respect to said first voltage potential to said selected metallization strip.

Claim 46

The read only memory of claim 34 wherein said first voltage potential and the nonselected aluminum metallization strips are at ground potential.

Claim 47

The read only memory of claim 34 wherein said first region of each semiconductor strip is coupled to a respective output terminal.

Claim 48

A semiconductor device comprising: an insulating substrate having an upper surface, a semiconductor strip having an upper and lower surface and positioned on said upper surface of said substrate, said strip having a first and second edge on either side of said strip extending from said lower surface to said upper surface, said semiconductor strip doped with impurities to exhibit material of a first type, said first and second edges of said strip doped at predetermined edge segments with impurities of a second type formed by introducing selected impurities through said first and second edges at said predetermined edge segments to form a plurality of spaced apart doped edge segments, said doped edge segments extending from said respective edge into said semiconductor strip in the range from 0.1 to 1 micrometer, said doped edge segments on said first and second edges having portions positioned opposite one another across said semiconductor strip, said semiconductor strip having an insulation layer over said upper surface and first and second edges, a plurality of spaced apart conductive strips extending over and transverse to said semiconductor strip and over doped edge segments positioned opposite one another to form a plurality of MOS transistors, said plurality of conductive strips coupled together, said plurality of MOS transistors and doped edge segments interconnected along said semiconductor strip to form a continuous conductive path at times said MOS transistors are conductive, means for making ohmic contact to one of said doped edge segments including aluminum deposited over said doped edge segment and over said semiconductor strip, and wherein said semiconductor strip is n type, and said aluminum over said semiconductor strip forms a Schottky barrier diode.

Claim 49

A semiconductor device comprising: an insulating substrate having an upper surface, a semiconductor strip having an upper and lower surface and positioned on said upper surface of said substrate, said strip having a first and second edge on either side of said strip extending from said lower surface to said upper surface, said semiconductor strip doped with impurities to exhibit material of a first type, said first and second edges of said strip doped at predetermined edge segments with impurities of a second type formed by introducing selected impurities through said first and second edges at said predetermined edge segments to form a plurality of spaced apart doped edge segments, said doped edge segments extending from said respective edge into said semiconductor strip in the range from 0.1 to 1 micrometer, said doped edge segments on said first and second edges having portions positioned opposite one another across said semiconductor strip, said semiconductor strip having an insulation layer over said upper surface and first and second edges, a plurality of spaced apart conductive strips extending over and transverse to said semiconductor strip and over doped edge segments positioned opposite one another to form a plurality of MOS transistors, said plurality of conductive strips coupled together, said plurality of MOS transistors and doped edge segments interconnected along said semiconductor strip to form a continuous conductive path at times said MOS transistors are conductive, means for making ohmic contact to one of said doped edge segments including aluminum deposited over said doped edge segment and over said semiconductor strip, and wherein said semiconductor strip is n type, and said aluminum over said semiconductor strip forms a Schottky barrier diode.

Claim 50

The semiconductor device of claim 37 wherein said semiconductor strip is four micrometers wide.

Claim 51

The semiconductor device of claim 37 wherein said plurality of conductive strips are four micrometers wide spaced apart by four micrometers.

Claim 52

The semiconductor device of claim 37 wherein a first of said MOS transistors has a drain formed by a first one of said doped edge segments on said first edge and a source formed by a second one of said doped edge segments on said second edge and spaced apart in the range from three to four micrometers.

Claim 53

The semiconductor device of claim 40 wherein said drain formed by said first one of said doped edge segments on said first edge extends at least another eight micrometers along said first edge to form the source of said second one of said MOS transistors and a drain formed by a third one of said doped edge segments on said second edge spaced by at least four micrometers from said second doped edge segment.

Claim 54

The semiconductor circuit of claim 15 wherein said first edge segment extends from said edge to a distance from 0.1 to 1 micrometer.

Claim 55

The semiconductor circuit of claim 15 wherein said first edge segment extends from said edge to a distance from 1000 to 3000 angstroms.

Claim 56

The semiconductor circuit of claim 17 wherein said first segment extends from said edge to a distance from 0.1 to 1 micrometer.

Claim 57

The semiconductor circuit of claim 17 wherein said first edge segment extends from said edge to a distance from 1000 to 3000 angstroms.

Claim 58

A semiconductor device comprising: an insulating substrate, a semiconductor layer having an upper and lower surface positioned on said insulating substrate, first and second spaced-apart sidewall surfaces extending between said upper and lower surface of said semiconductor layer, said semiconductor layer doped with impurities to exhibit a first type material, said semiconductor layer including first and second spaced apart regions of a second type formed by introducing selected impurities through selected areas of said first and second sidewall surfaces respectively, said first region and second region extending from said respective sidewall surface to a depth in the range from 0.1 to 1 micrometer, a layer of insulation positioned over said upper surface of said semiconductor layer extending between said first and second regions, a layer of conductive material positioned over said insulation layer and extending between said first and second regions, and first means for making ohmic contact to said first region including aluminum deposited on said first region and extending over onto said upper surface of said semiconductor layer, and second means for making ohmic contact to said second region.

Claim 59

A semiconductor device comprising: an insulating substrate, a semiconductor layer having an upper and lower surface positioned on said insulating substrate, first and second spaced-apart sidewall surfaces extending between said upper and lower surface of said semiconductor layer, said semiconductor layer doped with impurities to exhibit a first type material, said semiconductor layer including first and second spaced apart regions of a second type formed by introducing selected impurities through selected areas of said first and second sidewall surfaces respectively, said first region and second region extending from said respective sidewall surface to a depth in the range from 0.1 to 1 micrometer, a layer of insulation positioned over said upper surface of said semiconductor layer extending between said first and second regions, a layer of conductive material positioned over said insulation layer and extending between said first and second regions, and first means for making ohmic contact to said first region including aluminum deposited on said first region and extending over onto said upper surface of said semiconductor layer, and second means for making ohmic contact to said second region.

Claim 60

The semiconductor device of claim 3 wherein said predetermined depth from said respective edge is in the range from 0.1 to 1 mircometer.

Claim 61

The semiconductor device of claim 9 wherein said predetermined distance from said first sidewall surface is in the range from 0.1 to 1 micrometer.