US4533840A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Soliton sampler
Assignee: International Business Machines Corp
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Filing: 1982-09-13
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Granted: 1985-08-06
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Expires: 2002-09-13
Abstract
Abstract The invention is an all-soliton sampler for accessing very high speed circuits. A soliton is switched in two parallel branches, one including the device-under-test and the other including a programmable delay line implemented in soliton devices. The outputs of these two branches are used as controls to a soliton comparator which, in turn, controls a Josephson detector gate. This circuit permits a relatively slow rise time external trigger pulse to initiate an extremely narrow sampling pulse.
Inventors
- 👤 Tushar R. Gheewala
- 👤 Steven B. Kaplan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 16:46
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/195; G; G01; G01R; G01R13/00; G01R13/20; G01R13/22; G01R13/34; G01R13/342; H03K17/00; H03K17/51; H03K17/92; Y; Y10; Y10S; Y10S505/00; Y10S505/825; Y10S505/856; Y10S505/857; Y10S505/865
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
169 words
A sampling circuit, for a device-under-test, characterized by: (a) a soliton generator 2 to provide first and second soliton generator output nodes (Node 1, Node 2); (b) connection means (Node 3) for connecting a device-under-test 7 to the first output node (Node 1) of said soliton generator 2 to provide a test signal at a test signal node (Node 4); (c) time measurement means including a programmable delay line 8 and soliton comparator 9-14 connected to the second output node (Node 2) of said soliton generator 2, said soliton comparator having first and second soliton comparator output nodes (Node 5, Node 6); (d) termination means 13 connected to the first output node (Node 5) of said time measurement means 8-14; (e) detection means connected to the second output node of said time measurement means; (f) test control means 15 connected to said test signal node (Node 4) and connected across said soliton comparator 9-14; and (g) sampling control means 16 connected in control mode across said soliton comparator 9-14.
Claim 2
Dependent Claim
169 words
A sampling circuit, for a device-under-test, characterized by: (a) a soliton generator 2 to provide first and second soliton generator output nodes (Node 1, Node 2); (b) connection means (Node 3) for connecting a device-under-test 7 to the first output node (Node 1) of said soliton generator 2 to provide a test signal at a test signal node (Node 4); (c) time measurement means including a programmable delay line 8 and soliton comparator 9-14 connected to the second output node (Node 2) of said soliton generator 2, said soliton comparator having first and second soliton comparator output nodes (Node 5, Node 6); (d) termination means 13 connected to the first output node (Node 5) of said time measurement means 8-14; (e) detection means connected to the second output node of said time measurement means; (f) test control means 15 connected to said test signal node (Node 4) and connected across said soliton comparator 9-14; and (g) sampling control means 16 connected in control mode across said soliton comparator 9-14.
Claim 3
Dependent Claim
70 words
A sampling circuit according to claim 1, further characterized in that: said time measurement means (c) is made up of an array of long Josephson junctions 8.0-8.7 (FIG. 2), a respectively related array of control bias conductors C1-C8, and a counter 8.10 having a control setting and operably connected to said array of control bias conductors C1-C8 to provide for delay according to said control setting of said counter 8.10.
Claim 4
Dependent Claim
46 words
A sampling circuit according to claim 2, further characterized in that: said counter 8.10 of said time measurement means 8-14 may be kept in a room temperature range environment; and said array of long Josephson junctions 8.0-8.7 (FIG. 2) is kept in a cryogenic temperature envoronment.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-08-05 | 1989-02-04 | 1989-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-08-05 | 1993-02-04 | 1993-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-08-05 | 1997-02-04 | 1997-08-06 | $7700.00 | Window Closed / Lapsed |