Bidirectional one-half rate counter

Claim 2

A half-rate bidirectional counting circuit comprising an up/down counter having an UP input and a DOWN input, first and second gate means connected with a source of UP pulses and a source of DOWN pulses, respectively, for respectively gating said UP and DOWN pulses to said UP and DOWN inputs, bistable means for alternately enabling said first and second gate means in response to either an UP or DOWN pulse and means for initializing said bistable means and said counter.

Claim 3

A bidirectional counting circuit having a first circuit input and a second circuit input for receiving pulses representing motion of a device in first and second directions, respectively, counter means having a first counter input and a second counter input, said counter means being incremented in response to a pulse at said first counter input and decremented in response to a pulse at said second counter input, first gate means connected between said first circuit input and said first counter input, second gate means connected between said second circuit input and said second counter input, bistable circuit means for alternately enabling said first and second gate means in response to pulses at either said first or second circuit inputs, means for initializing said counter means and said bistable circuit means, first display means for displaying the content of said counter means, and second display means for displaying the digit "0" or the digit "5" depending upon the state of said bistable circuit means.

Claim 4

A bidirectional counting circuit having a first circuit input and a second circuit input for receiving pulses representing motion of a device in first and second directions, respectively, counter means having a first counter input and a second counter input, said counter means being incremented in response to a pulse at said first counter input and decremented in response to a pulse at said second counter input, first gate means connected between said first circuit input and said first counter input, second gate means connected between said second circuit input and said second counter input, bistable circuit means for alternately enabling said first and second gate means in response to pulses at either said first or second circuit inputs, means for initializing said counter means and said bistable circuit means, first display means for displaying the content of said counter means, and second display means for displaying the digit "0" or the digit "5" depending upon the state of said bistable circuit means.

Claim 5

A half rate bidirectional counting circuit comprising an up/down counter having an UP input and a DOWN input, first and second gate means connected with a source of UP and DOWN pulses respectively for respectively gating said UP and DOWN pulses to said UP and DOWN inputs, a synchronizing flip-flop for alternately enabling said first and second gate means in response to either an UP or DOWN pulse, up/down indicator means, an up/down flip-flop responsive to said UP and DOWN pulses for controlling said indicator means, circuit means for initializing said counter means, said synchronzing flip-flop, and said up/down flip-flop in response to a reference pulse, means for displaying the content of said counter means and for displaying the digit "0" or the digit "5" as a suffix to the displayed counter content depending upon the state of said synchronizing flip-flop.

Claim 6

A half rate bidirectional counting circuit comprising an up/down counter having an UP input and a DOWN input, first and second gate means connected with a source of UP and DOWN pulses respectively for respectively gating said UP and DOWN pulses to said UP and DOWN inputs, a synchronizing flip-flop for alternately enabling said first and second gate means in response to either an UP or DOWN pulse, up/down indicator means, an up/down flip-flop responsive to said UP and DOWN pulses for controlling said indicator means, circuit means for initializing said counter means, said synchronzing flip-flop, and said up/down flip-flop in response to a reference pulse, means for displaying the content of said counter means and for displaying the digit "0" or the digit "5" as a suffix to the displayed counter content depending upon the state of said synchronizing flip-flop.

Claim 7

The circuit of claim 3 further comprising a manually operative zeroing switch, said initializing circuit means being responsive to operation of said switch, means responsive to a predetermined state of said synchronizing flip-flop for disabling said switch.