Patent US4532604A successfully refreshed from Google Patents.
US4532604A
Expired / Lapsed
US
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Predistortion circuit
Assignee: Ampex Corp
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Filing: 1982-09-16
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Granted: 1985-07-30
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Expires: 2002-09-16
Abstract
Abstract A predistortion error signal, corresponding to the third harmonic of an input signal, is generated by obtaining the absolute value of the input signal and multiplying it by the input signal of given sign to provide the square of the latter times the sign of the input signal. The squared signal then is multiplied by the absolute value of the input signal again to provide the desired cube of the input signal.
Inventors
- 👤 Jay S. Baker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:53
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/02
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
95 words
A circuit for generating a predistortion signal from an input signal of given sign, comprising: rectifier means for generating the absolute value of the input signal; first operational transconductance amplifier means receiving the input signal of given sign and responsive to the absolute value for generating the square of the input signal times the sign of the input signal; and second operational transconductance amplifer means coupled to the first operational transconductance amplifier means and responsive a second time to the absolute value for generating the cube of the input signal corresponding to the predistortion signal.
Claim 2
Dependent Claim
95 words
A circuit for generating a predistortion signal from an input signal of given sign, comprising: rectifier means for generating the absolute value of the input signal; first operational transconductance amplifier means receiving the input signal of given sign and responsive to the absolute value for generating the square of the input signal times the sign of the input signal; and second operational transconductance amplifer means coupled to the first operational transconductance amplifier means and responsive a second time to the absolute value for generating the cube of the input signal corresponding to the predistortion signal.
Claim 3
Dependent Claim
38 words
The circuit of claim 1 wherein: said rectifier means include a full wave rectifier coupled to the input signal; and said first and second operational transconductance amplifier means include gain control stages responsive to the full wave rectifier.
Claim 4
Dependent Claim
29 words
The circuit of claim 2 wherein the first and second operational transconductance amplifier means further include: first and second operational amplifiers respectively, each coupled to respective gain control stages.
Claim 5
Dependent Claim
43 words
The circuit of claim 3 wherein: said first operational amplifier includes an inverting input coupled to the respective gain control stage; and said second operational amplifier includes an inverting input coupled to the gain control stage of the second operational transconductance amplifier means.
Claim 6
Dependent Claim
35 words
The circuit of claim 3 including: offset adjustment means coupled to either of said gain control stages of said first and second operational transconductance amplifier means for nulling error signals due to internal circuit imbalance.
Claim 7
Dependent Claim
40 words
The circuit of claim 3 wherein said rectifier means further include: a second full wave rectifier coupled to the input signal; and said gain control stages are coupled to a respective one of the first and second full wave rectifiers.
Claim 8
Dependent Claim
28 words
The circuit of claim 3 including: an amplifier stage coupled to the second operational transconductance amplifier means for varying the predistortion signal in response to predetermined predistortion conditions.
Claim 9
Dependent Claim
91 words
A circuit for generating a third harmonic signal of an input signal of given sign, comprising: first means including a full wave rectifier for generating the absolute value of the input signal; second means including two-quadrant multiplier means coupled to the input signal and responsive to the first means for supplying the square of the input signal times the sign of the input signal; and third means including two-quadrant multiplier means coupled to the second means and also responsive to the first means for supplying the cube of the input signal.
Claim 10
Dependent Claim
91 words
A circuit for generating a third harmonic signal of an input signal of given sign, comprising: first means including a full wave rectifier for generating the absolute value of the input signal; second means including two-quadrant multiplier means coupled to the input signal and responsive to the first means for supplying the square of the input signal times the sign of the input signal; and third means including two-quadrant multiplier means coupled to the second means and also responsive to the first means for supplying the cube of the input signal.
Claim 11
Dependent Claim
34 words
The circuit of claim 8 wherein the two-quadrant multiplier means include: a current controlled gain stage responsive to the full wave rectifier; and operational amplifier means coupled to a respective current controlled gain stage.
Claim 12
Dependent Claim
56 words
The circuit of claim 8 wherein the two-quadrant multiplier means include: a first current controlled gain stage coupled to receive the input signal; a first operational amplifier coupled to the first gain stage; a second current controlled gain stage coupled to the first operational amplifier; and a second operational amplifier coupled to the second gain stage.
Claim 13
Dependent Claim
25 words
The circuit of claim 10 wherein: the first and second current controlled gain stages vary the signal thereto in response to the full wave rectifier.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-07-29 | 1989-01-28 | 1989-07-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-07-29 | 1993-01-28 | 1993-07-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-07-29 | 1997-01-28 | 1997-07-30 | $7700.00 | Window Closed / Lapsed |