US4042815A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electronic multipliers
Assignee: Ferranti International PLC
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Filing: 1976-01-16
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Granted: 1977-08-16
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Expires: 1996-01-16
Abstract
Abstract A multiplier circuit arrangement comprises two parallel paths for the same signal, one of the paths being associated with signal level adjusting means; and means responsive to inbalance of d.c. components including any in said parallel paths, the inbalance being in accordance with a d.c. signal in a third signal path, to produce a control signal for varying the signal level adjusting means to reduce the imbalance, so that a.c. components in said parallel paths will be unbalanced to an extent proportional to the d.c. signal in said third path.
Inventors
- 👤 Kenneth Robson Brown
- 👤 Colin Keith Sharp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 20:52
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/16; G06G7/161; G06G7/22
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
141 words
An electronic multiplier circuit comprising a first input terminal to which an a.c. signal is applied, a junction point, two parallel paths connected between the input terminal and the junction point, signal level adjusting means included in one of said parallel paths, a second input terminal to which a d.c. signal is applied, a third path connected to said second input terminal, an output terminal, and control means connected between the junction point and the output terminal and responsive to any imbalance of d.c. components in said parallel paths and to a d.c. signal in the third path to produce a control signal for varying the signal level adjusting means so as to reduce said d.c. imbalance, whereby a.c. components in said two parallel paths are unbalanced to an extent proportional to the d.c. signal applied to the second input terminal.
Claim 2
Dependent Claim
141 words
An electronic multiplier circuit comprising a first input terminal to which an a.c. signal is applied, a junction point, two parallel paths connected between the input terminal and the junction point, signal level adjusting means included in one of said parallel paths, a second input terminal to which a d.c. signal is applied, a third path connected to said second input terminal, an output terminal, and control means connected between the junction point and the output terminal and responsive to any imbalance of d.c. components in said parallel paths and to a d.c. signal in the third path to produce a control signal for varying the signal level adjusting means so as to reduce said d.c. imbalance, whereby a.c. components in said two parallel paths are unbalanced to an extent proportional to the d.c. signal applied to the second input terminal.
Claim 3
Dependent Claim
16 words
A circuit according to claim 1, wherein the third path is also connected to the junction.
Claim 4
Dependent Claim
33 words
A circuit according to claim 2, comprising at least one further path connected to said junction for a further d.c. input signal to produce a product involving the sum of the d.c. inputs.
Claim 5
Dependent Claim
23 words
A circuit according to claim 1, wherein the third path is connected to directly affect the a.c. signal level in the one path.
Claim 6
Dependent Claim
14 words
A circuit according to claim 1, wherein the one path includes signal inverting means.
Claim 7
Dependent Claim
17 words
A circuit according to claim 5, wherein the third path is input to the signal inverting means.
Claim 8
Dependent Claim
31 words
A circuit according to claim 6, comprising a further path connected to the junction for a further d.c. input signal to produce a product involving the difference between the d.c. inputs.
Claim 9
Dependent Claim
20 words
A circuit according to claim 1, wherein the means responsive to imbalance passes an a.c. component proportional to said imbalance.
Claim 10
Dependent Claim
35 words
A circuit according to claim 8, wherein said means responsive to imbalance comprises a summing amplifier having an a.c. feedback path to a virtual earth input to which said parallel paths are also jointly connected.
Claim 11
Dependent Claim
26 words
A circuit according to claim 1, wherein the signal level adjusting means comprises a field effect transistor having the control signal applied to its gate electrode.
Claim 12
Dependent Claim
40 words
A circuit according to claim 1, wherein the other of the parallel paths has an a.c. shunt for adjusting the path resistance in accordance with differences of resistance presented by the signal level adjusting means to a.c. and d.c. signals.
References Cited (Backward Citations)
US3070309A
Cited
US3294961A
Cited
US3439270A
Cited
US3414721A
Cited
US3448297A
Cited
US3631262A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-15 | 1981-02-14 | 1981-08-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-15 | 1985-02-14 | 1985-08-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-15 | 1989-02-14 | 1989-08-16 | $7700.00 | Window Closed / Lapsed |