Pulse width modulation type digital to analog converter

Claim 2

A DA converter comprising: storing means for temporarily storing N-bit digital data to be DA converted; digital value string generating means for counting pulses of a predetermined frequency to sequentially binary numbers, said generating means comprising an n-bit (n<N+1) binary counter; a detection circuit which is connected to said n-bit binary counter, for detecting when a count of said n-bit binary counter has reached first and second preset numbers and outputtting a clock signal when the count of said n-bit binary counter reaches the first preset number and outputting a latch signal when the count of said n-bit binary counter reaches the second preset number; an (N-n) binary counter which is connected to said detection circuit and for incrementing its count thereof upon receipt of said clock signal from said detection circuit; N-bit comparing means connected to said storing means and said digital value string generating means, for sequentially comparing each of the plurality of digital value strings with the digital data so as to output pulses corresponding to the number of the digital value strings, said N-bit comparing means including: a first comparator for comparing the count from said N-bit counter, in an inverted order, with the lower significant n-bits of the N-bit data to be converted, a latch circuit which is connected to the outputs of said first comparator and said detection circuit or latching an output from said first comparator in response to the latch signal from said detection circuit, and a second comparator which is connected to the output of said latch circuit, for comparing the contents of the n-bit counter with the higher significant n-bits of the N-bit data to be converted and for producing a comparison output signal with a control priority over an output from said latch circuit; and smoothing means, connected to said N-bit comparing means, for converting the output of said N-bit comparing means into an analog signal representing said N-bit digital clock.

Claim 3

A DA converter according to claim 1, wherein said n-bit binary counter comprises a synchronous binary counter.

Claim 4

A DA converter comprising: storing means for temporarily storing N-bit digital data to be DA converted; digital value string generating means for counting pulses of a predetermined frequency to generate a plurality of dispersed digital value strings to be compared with the digital data within one conversion period and in correspondence with digital values varying within the conversion period; N-bit comparing means, connected to said storing means and said digital value string generating means, for sequentially comparing each of the plurality of digital value strings with the digital data so as to output pulses corresponding to the number of the digital value strings, said N-bit comparing means coupled to the outputs of said n-bit binary counter for receiving the upper significant (N-n+1)th to Nth bits, and of said (N-n) bit binary counter for receiving the least significant bit to (N-n)th bits; and smoothing means connected to said N-bit comparing means, for converting the pulses generated within the conversion period by said N-bit comparing means into an analog signal, wherein said digital value string generating means comprises an n-bit (n-1<N) binary counter for counting the pulses of the predetermined frequency to sequentially generate binary numbers, a detection circuit which is connected to said n-bit binary counter which detects if a count of said n-bit binary counter has reached first and second preset numbers and which outputs a clock signal when the count of said n-bit binary counter reaches the first preset number and outputs a latch signal when the count of said n-bit binary counter reaches the second preset number, and an (N-n) bit binary counter which is connected to said detection circuit and which increments a count thereof by one when the clock signal is received, said n-bit binary counter supplying an output thereof to upper significant (N-n+1)th to Nth bits of said N-bit comparing means, and said (N-n) bit binary counter supplying an inverted output to the least significant bit to (N-n)th bits of said N-bit comparing means.

Claim 5

A DA converter comprising: storing means for temporarily storing N-bit digital data to be DA converted; digital value string generating means for counting pulses of a predetermined frequency to generate a plurality of dispersed digital value strings to be compared with the digital data within one conversion period and in correspondence with digital values varying within the conversion period; N-bit comparing means, connected to said storing means and said digital value string generating means, for sequentially comparing each of the plurality of digital value strings with the digital data so as to output pulses corresponding to the number of the digital value strings, said N-bit comparing means coupled to the outputs of said n-bit binary counter for receiving the upper significant (N-n+1)th to Nth bits, and of said (N-n) bit binary counter for receiving the least significant bit to (N-n)th bits; and smoothing means connected to said N-bit comparing means, for converting the pulses generated within the conversion period by said N-bit comparing means into an analog signal, wherein said digital value string generating means comprises an n-bit (n-1<N) binary counter for counting the pulses of the predetermined frequency to sequentially generate binary numbers, a detection circuit which is connected to said n-bit binary counter which detects if a count of said n-bit binary counter has reached first and second preset numbers and which outputs a clock signal when the count of said n-bit binary counter reaches the first preset number and outputs a latch signal when the count of said n-bit binary counter reaches the second preset number, and an (N-n) bit binary counter which is connected to said detection circuit and which increments a count thereof by one when the clock signal is received, said n-bit binary counter supplying an output thereof to upper significant (N-n+1)th to Nth bits of said N-bit comparing means, and said (N-n) bit binary counter supplying an inverted output to the least significant bit to (N-n)th bits of said N-bit comparing means.

Claim 6

A DA converter according to claim 3, wherein said N-bit comparing means comprises a first comparator for comparing contents of the least significant bit to (N-n)th bit; a latch circuit which is connected to said comparator and said detection circuit and which latches an output from said first comparator in response to the latch signal; and a second comparator whicn is connected to said latch circuit and which compares the contents of upper significant (N-n+1)th to Nth bits and produces a comparison output with a priority over an output from said latch circuit.