US4532005A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Device lithography using multi-level resist systems
Assignee: Nokia Bell Labs
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Filing: 1984-05-21
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Granted: 1985-07-30
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Expires: 2004-05-21
Abstract
Abstract In order to hard-bake the bottom resist layer of a tri-level resist system for patterning a device wafer, the resist is subjected to a positive ramp heating step (of increasing ambient temperatures).
Inventors
- 👤 Michael J. Grieco
- 👤 Laura P. Hale
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:38
CPC Classifications
G; G03; G03F; G03F7/00; G03F7/16; G03F7/168; G03F7/004; G03F7/09; G03F7/094; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/948; Y10S438/95
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
110 words
In a process for patterning a device wafer using a multi-level resist system having a bottom layer of novolac-type resist, the step of ramp heating the bottom resist layer for a time duration of between about 5 minutes and about 30 minutes, comprising subjecting the bottom resist layer to an initial ambient temperature of between about 150 degrees C. and about 180 degrees C. and thereafter to a final ambient temperature of between about 230 degrees C. and about 270 degrees C., whereby the bottom resist layer is subjected to ambient temperatures between about 150 degrees C. and about 180 degrees C. for at least one-quarter of the time duration.
Claim 2
Dependent Claim
110 words
In a process for patterning a device wafer using a multi-level resist system having a bottom layer of novolac-type resist, the step of ramp heating the bottom resist layer for a time duration of between about 5 minutes and about 30 minutes, comprising subjecting the bottom resist layer to an initial ambient temperature of between about 150 degrees C. and about 180 degrees C. and thereafter to a final ambient temperature of between about 230 degrees C. and about 270 degrees C., whereby the bottom resist layer is subjected to ambient temperatures between about 150 degrees C. and about 180 degrees C. for at least one-quarter of the time duration.
Claim 3
Dependent Claim
23 words
The process of claim 1 in which a silicon dioxide layer is deposited upon the bottom resist layer subsequent to the ramp heating.
Claim 4
Dependent Claim
35 words
The process of claim 2 in which the initial ambient temperature is about 180 degrees C., the final ambient temperature is about 250 degrees C., and the time duration is about 6 to 10 minutes.
Claim 5
Dependent Claim
38 words
The process of claim 3 in which the resist layer is subjected to an intermediate ambient temperature of about 225 degrees C. after having been subjected to the initial, and before being subjected to the final, ambient temperature.
Claim 6
Dependent Claim
33 words
The process of claim 3 in which the ramp heating is achieved by moving the device wafer from an ambient maintained at the initial temperature to another ambient maintained at the final temperature.
Claim 7
Dependent Claim
23 words
The process of claim 5 in which a silicon dioxide layer is deposited upon the bottom resist layer subsequent to the ramp heating.
Claim 8
Dependent Claim
23 words
The process of claim 3 in which a silicon dioxide layer is deposited upon the bottom resist layer subsequent to the ramp heating.
Claim 9
Dependent Claim
23 words
The process of claim 2 in which a silicon dioxide layer is deposited upon the bottom resist layer subsequent to the ramp heating.
Claim 10
Dependent Claim
40 words
The process of claim 1 in which the ramp heating comprises successively the initial ambient temperature of about 180 degrees C., an intermediate ambient temperature of about 225 degrees C., and the final ambient temperature of about 250 degrees C.
Claim 11
Dependent Claim
23 words
The process of claim 9 in which a silicon dioxide layer is deposited upon the bottom resist layer subsequent to the ramp heating.
Claim 12
Dependent Claim
24 words
The process of claim 10 in which the time duration of the ramp heating is in the range of about 6 to 10 minutes.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-07-29 | 1989-01-28 | 1989-07-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-07-29 | 1993-01-28 | 1993-07-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-07-29 | 1997-01-28 | 1997-07-30 | $7700.00 | Window Closed / Lapsed |