Validity checking arrangement for extended memory mapping of external devices

Claim 1

In a telecommunications switching system, a CPU accesses a plurality of external devices via a plurality of unit signals in a memory mapped access, a validity checking arrangement for determining said CPU access to invalid ones of said plurality of external devices, said validity checking arrangement comprising: changeable memory means being connected to said CPU for dynamically storing words representing an access status for each of said plurality of external devices, said changeable memory means being operated to store said words; said access status word including identical half words for each valid external device; said access status word including non-identical half words of a predefined value for each invalid external device; said changeable memory means being further operated in response to said unit signal of said CPU, representing a particular device access, to read out and to transmit one selected access status word of said plurality of status words; means for comparing connected to said changeable memory means and to said CPU and being operated in response to said selected access status word to perform a bit-for-bit comparison and to provide an alarm signal for any bit miscomparison of said halves of aaid selected access status word, for indicating an invalid unit signal selection by said CPU; logic means connected between said means for comparing and said CPU; said means for comparing connected to said logic means and being further operated to transmit said one selected access status word half to said logic means in response to a bit-for-bit equality comparison of said selected access status word halves; and said logic means being operated in response to said transmitted access status half words to configure said external devices and to transmit a ready signal to said CPU.