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US4531202A
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Semiconductor nonvolatile read only memory device
Assignee: Toshiba Corp
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Filing: 1982-01-29
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Granted: 1985-07-23
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Expires: 2002-01-29
Abstract
Abstract A semiconductor nonvolatile read only memory device has a voltage applying circuit which sets all word lines at ground potential in a stand-by mode and sets only a selected word line at a high level in an active mode. The word lines are connected to the gates of semiconductor nonvolatile memory transistors. Each of the memory transistors has the source (or drain) grounded and the drain (or source) connected to output lines. In a stand-by mode, the voltage applying circuit keeps all the word lines at ground potential. In an active mode, the voltage applying circuit applies a high level voltage only to the selected word line. The memory transistor connected to the selected word line produces data of "0" or "1" to the output line.
Inventors
- 👤 Shigeyoshi Watanabe
- 👤 Sumio Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 08:21
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/08
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
139 words
A semiconductor nonvolatile read only memory device comprising: semiconductor nonvolatile memory transistors, a reference voltage being applied to the sources of said transistors; word lines connected to the gates of said transistors; output lines connected to the drains (or sources) of said transistors; and voltage applying means connected to said word lines for applying said reference voltage to said word lines in a stand-by mode, and applying a readout voltage to only selected one of said word lines in a readout mode; write-in voltage terminal; and writing means connected between said write-in voltage terminal and said word lines for applying a write-in voltage to only a selected one of said word lines in a write-in mode and preventing current from flowing from said write-in voltage terminal to said word lines in any operation mode other than a write-in mode.
Claim 2
Dependent Claim
139 words
A semiconductor nonvolatile read only memory device comprising: semiconductor nonvolatile memory transistors, a reference voltage being applied to the sources of said transistors; word lines connected to the gates of said transistors; output lines connected to the drains (or sources) of said transistors; and voltage applying means connected to said word lines for applying said reference voltage to said word lines in a stand-by mode, and applying a readout voltage to only selected one of said word lines in a readout mode; write-in voltage terminal; and writing means connected between said write-in voltage terminal and said word lines for applying a write-in voltage to only a selected one of said word lines in a write-in mode and preventing current from flowing from said write-in voltage terminal to said word lines in any operation mode other than a write-in mode.
Claim 3
Dependent Claim
34 words
A semiconductor nonvolatile read only memory device according to claim 1, further comprising: voltage setting means connected to said output lines for setting said output lines at a specified voltage in a stand-by mode.
Claim 4
Dependent Claim
20 words
A semiconductor nonvolatile read only memory device according to claims 1 or 2, wherein said reference voltage is ground potential.
Claim 5
Dependent Claim
143 words
A semiconductor nonvolatile read only memory device according to claim 1, wherein said writing means comprises a depletion MOSFET having the gate and the source (or drain) connected to said word line and an enhancement MOSFET having the source (or drain) connected to the drain (or source) of said depletion MOSFET, and the drain (or source) to said write-in terminal, thereby, in a writing operation, allowing a raised voltage higher than a voltage at said write-in terminal to be applied to the gate of said enhancement MOSFET to apply the same voltage as that of said write-in terminal to said word line via said depletion MOSFET, while, in any operation other than writing, permitting a low level voltage to be applied to the same gate to prevent current from being supplied from said write-in terminal through said depletion MOSFET to said word line.
Claim 6
Dependent Claim
75 words
A semiconductor nonvolatile read only memory device according to claims 1 or 2, wherein said voltage applying means comprises a pre-decoder including a plurality of MOSFETs, said decoder keeping said word lines at said reference voltage in a stand-by mode, and raising the potential on only one of said word lines selected up to substantially a power source voltage and while keeping said word lines not selected at said reference voltage in an active mode.
Claim 7
Dependent Claim
76 words
A semiconductor nonvolatile read only memory device according to claims 1 or 2, wherein said voltage applying means comprises a direct decoder including a plurality of MOSFETs, said direct decoder keeping said word lines at said reference voltage in a stand-by mode, and raising the potential on only one of said word lines selected up to substantially a power source voltage, while keeping said word lines not selected at said reference voltage in an active mode.
Claim 8
Dependent Claim
91 words
A semiconductor nonvolatile read only memory device according to claim 2 wherein said voltage setting means comprises a pre-decoder including a plurality of MOSFETs whose drains are connected to said output lines and whose sources are connected to receive said reference voltage, said pre-decoder being so constructed as to turn on said MOSFETS in a stand-by mode, thereby keeping said output lines at said reference voltage, and to turn off said MOSFETs in an active mode, thereby obtaining data stored in said semiconductor nonvolatile memory transistor selected onto said output line.
Claim 9
Dependent Claim
93 words
A semiconductor nonvolatile read only memory device according to claim 2 wherein said voltage setting means comprises a direct decoder including a plurality of MOSFETs whose drains are connected to said output lines and whose sources are connected to receive said reference voltage, said direct decoder being so constructed as to turn on said MOSFETs in a stand-by mode, thereby keeping said output lines at said reference voltage, and to turn off said MOSFETs in an active mode, thereby obtaining data stored in said semiconductor nonvolatile memory transistor selected onto said output line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-07-22 | 1989-01-21 | 1989-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-07-22 | 1993-01-21 | 1993-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-07-22 | 1997-01-21 | 1997-07-23 | $7700.00 | Window Closed / Lapsed |