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US4528744A
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US
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Method of manufacturing a semiconductor device
Assignee: Toshiba Corp
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Filing: 1983-04-05
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Granted: 1985-07-16
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Expires: 2003-04-05
Abstract
Abstract A method of manufacturing a semiconductor device which comprises the steps of forming an interconnection layer through an insulating film on a semiconductor substrate, and connecting the diffusion interconnection region in the surface portion of said substrate to said interconnection layer by growing a metal or metal semiconductor compound on the surface of said substrate and the interconnection layer.
Inventors
- 👤 Tadashi Shibata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 19:33
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/20; H10W20/01; H10W20/031; H10W20/064; H10W20/066; H10W20/0698; H10W20/40; H10W20/41; H10W20/44; H10W20/4451; Y; Y10; Y10S; Y10S438/00; Y10S438/98
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
160 words
A method of manufacturing a semiconductor device comprising the steps of: forming an insulating film on a semiconductor substrate; forming a gate electrode and an interconnection layer on said insulating film; introducing an impurity of conductivity type opposite to that of said substrate into said substrate to form a source, drain and diffusion interconnection regions; forming an insulating layer on the entire surface of said insulating film, gate electrode and interconnection layer; etching said insulating layer and insulating film by an anisotropic etching, thus leaving insulating layers on the side walls of said gate electrode and interconnection layer; removing that portion of the insulating layer on the side walls of the interconnection layer which adjoins the diffusion interconnection region in the surface portion of said substrate; and connecting the diffusion interconnection region to said interconnection layer by growing a substance selected from the group consisting of metals and metal semiconductors on the surface of said substrate and the interconnection layer.
Claim 2
Independent Claim
160 words
A method of manufacturing a semiconductor device comprising the steps of: forming an insulating film on a semiconductor substrate; forming a gate electrode and an interconnection layer on said insulating film; introducing an impurity of conductivity type opposite to that of said substrate into said substrate to form a source, drain and diffusion interconnection regions; forming an insulating layer on the entire surface of said insulating film, gate electrode and interconnection layer; etching said insulating layer and insulating film by an anisotropic etching, thus leaving insulating layers on the side walls of said gate electrode and interconnection layer; removing that portion of the insulating layer on the side walls of the interconnection layer which adjoins the diffusion interconnection region in the surface portion of said substrate; and connecting the diffusion interconnection region to said interconnection layer by growing a substance selected from the group consisting of metals and metal semiconductors on the surface of said substrate and the interconnection layer.
Claim 3
Dependent Claim
16 words
The method according to claim 1, wherein said interconnection layer is formed of an impurity-doped poly-silicon.
Claim 4
Dependent Claim
22 words
The method according to claim 1, wherein said interconnection layer is formed by patterning the poly-silicon layer together with a gate electrode.
Claim 5
Dependent Claim
26 words
The method according to claim 1, wherein said diffusion interconnection region is an extension of at least one of a source region and a drain region.
Claim 6
Dependent Claim
62 words
A method according to claim 1, wherein said growing step includes the steps of heating said semiconductor substrate at a temperature above 200° C., surrounding said semiconductor substrate with a metal halide gas or a mixture of a metal halide gas and a reducing gas, and depositing a metal film on the exposed surfaces of said semiconductor substrate and said interconnection layer.
Claim 7
Dependent Claim
27 words
A method according to claim 5, wherein the metal is a member selected from the group consisting of W, Pd, Pt, Ni, Mo, Nb, Ta and Ti.
Claim 8
Dependent Claim
24 words
The method according to claim 1, wherein said interconnection layer is formed of a two-layer structure of an impurity-doped poly-silicon and a metal silicide.
Claim 9
Dependent Claim
12 words
The method according to claim 1, wherein said substance is a metal.
Claim 10
Dependent Claim
13 words
The method according to claim 1 wherein said substance is a metal semiconductor.
Claim 11
Dependent Claim
62 words
A method according to claim 1, wherein said growing step includes the steps of depositing a metal on the entire surface of the structure, forming a metal silicide film on the surfaces of the semiconductor substrate and the interconnection layer by reacting the semiconductor substrate and the interconnection layer with the metal which is in contact with them, and eliminating unreacted metal.
Claim 12
Dependent Claim
23 words
A method according to claim 10, wherein the reaction between the metal and the silicon is performed by a method of thermal annealing.
Claim 13
Dependent Claim
34 words
A method according to claim 10, wherein the reaction between the metal and silicon is performed by ion-implanting an impurity which has a conductivity type opposite to the conductivity type of said semiconductor substrate.
Claim 14
Dependent Claim
28 words
A method according to claim 10, wherein the metal is a member selected from the group consisting of W, Pd, Pt, Ni, Mo, Nb, Ta, Ir and Ti.
Claim 15
Dependent Claim
23 words
A method according to claim 10, wherein the reaction between the metal and silicon is performed by a method of laser beam irradiation.
Claim 16
Dependent Claim
23 words
A method according to claim 10, wherein the reaction between the metal and silicon is performed by a method of electron beam irradiation.
Claim 17
Dependent Claim
21 words
A method according to claim 10, wherein the reaction between the metal and silicon is performed by a method of ion-implantation.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-07-15 | 1989-01-14 | 1989-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-07-15 | 1993-01-14 | 1993-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-07-15 | 1997-01-14 | 1997-07-16 | $7700.00 | Window Closed / Lapsed |