Integrated circuit device accepting inputs and providing outputs at the levels of different logic families

Claim 2

In a semiconductor chip, an integrated circuit device comprising: (a) means for accepting the input of first signals at the level of a first logic family to produce second signals at the level of said first logic family; (b) means for accepting the input of third signals at the level of a second logic family to produce fourth signals at the level of said first logic family; (c) circuit means, operative at the level of said first logic family for operating upon said second signals and said fourth signals to produce fifth signals and sixth signals, respectively, at the level of said first logic family; (d) means for providing an output of seventh signals at the level of said first logic family in response to said fifth signals; and (e) means for providing an output of eighth signals at the level of said second logic family in response to said sixth signals.

Claim 3

An integrated circuit device, according to claim 1, wherein said means for accepting the input of third signals comprises means for translating the level of said third signals from the level of said second logic family to the level of said first logic family.

Claim 4

An integrated circuit device, according to claim 2, wherein said means for accepting the input of said first signals comprises means for directly coupling said first signals to said circuit means at the level of said first logic family.

Claim 5

An integrated circuit device, according to claim 2, wherein said means for accepting the input of said first signals comprises buffer means for receiving said first signals and producing said second signals for said circuit means.

Claim 6

An integrated circuit device, according to claim 1, wherein said means for providing an output of eighth signals comprises means for translating said sixth signals from the level of said first logic family to the level of said second logic family.

Claim 7

An integrated circuit device, according to claim 5, wherein said means for providing an output of seventh signals includes buffer means for receiving said fifth signals from said circuit means and providing an output external to the chip.

Claim 8

An integrated circuit device in accordance with any one of claims 1-6 wherein said first logic family is emitter coupled logic and said second logic family is transistor-transistor logic.

Claim 9

An integrated circuit device, in accordance with claim 1, wherein said circuit means comprises logic circuit means.

Claim 10

An integrated circuit device, in accordance with claim 1, wherein said circuit means comprises memory circuit means.

Claim 11

An integrated circuit device, in accordance with claim 1, wherein said circuit means comprises logic means and memory means.

Claim 12

An integrated circuit device in accordance with claim 1 wherein said means for providing an output of eighth signals at the level of said second logic family is a TTL to ECL translator comprising: a constant current source transistor having its emitter connected to TTL ground; a first pair of bipolar transistors having their emitters connected in common to the collector of said constant current source transistor, their collectors for connection to the power supply level TTL V CC , the base of one transistor having a fixed reference voltage applied thereto and the base of the other transistor being applied to the TTL input line, so that said pair of bipolar transistors conduct differentially as the TTL input level is above or below said fixed reference voltage; a second pair of bipolar transistors having their bases connected to the collectors of respective ones of said first pair of bipolar transistors, having their collectors connected to TTL V CC and having their emitters connected through respective resistor to the ECL V EE line; a second constant current source transistor having its emitter connected to said ECL V EE line; a third pair of bipolar transistors having their emitters connected in common to the collector of said second constant current source transistor, their collectors for connection to the power supply level ECL ground, and having their bases connected, respectively, to the emitters of respective ones of said second pair of bipolar transistors; and a pair of output transistors having their bases connected to respective ones of the collectors of said third pair of bipolar transistors, their collectors connected in common to ECL ground and their emitters connected through current stabilizing means to ECL V EE , the emitters of said pair of output transistors serving as the inverting and non-inverting ECL outputs.

Claim 13

An integrated circuit device in accordance with claim 1 wherein said means for accepting the input of third signals at the level of a second logic family to produce fourth signals at the level of said first logic family comprises an ECL to TTL translator, including a constant current source transistor having its emitter connected to the ECL V EE reference level and its base connected to a bandgap reference voltage; a pair of bipolar transistors having their emitters connected in common to the collector of said constant current source transistor and having their collectors connected, respectively, to ECL ground and to a differential drive circuit, said differential drive circuit comprising a pullup output transistor having its emitter connected to the TTL output line and its collector connected to TTL V CC ; a pulldown output transistor having its collector connected to the TTL output line and its emitter connected to TTL ground; a first base drive transistor having its emitter connected to the base of said pullup output transistor and having its collector connected to the collector of said pullup output transistor; a second base drive transistor having its emtter connected to the base of said pulldown output transistor and having its collector connected to TTL V CC through a resistor, to the base of said first base drive transistor and to the base of said pullup output transistor through a diode; and means in response to current from said constant current source conducted through the one of said pair of bipolar transistors connected to said differential drive circuit to turn said first base drive transistor on or off, and thereby turn said second base drive transistor off or on to either pull up or pull down said TTL output level in accordance with an ECL input level applied to the base of at least one of said pair of bipolar transistors.