Patent US4523216A successfully refreshed from Google Patents.
US4523216A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS device with high density wiring layout
Assignee: Toshiba Corp
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Filing: 1982-03-02
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Granted: 1985-06-11
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Expires: 2002-03-02
Abstract
Abstract A CMOS device has P- and N-channel transistors sandwiching an isolation region formed on a semiconductor substrate. The drain regions, as well as the gate regions, of both transistors are connected by respective wiring layers made of polycrystalline silicon. Electrical contacts between the drain-connecting polycrystalline silicon wiring layer and each of the drain regions have a symmetrical structure in both transistors. In the electrical contacts, impurity diffusion regions having the same conductivity type as the drain regions and being contiguous with the drain regions are formed on the semiconductor substrate and the well region under the polycrystalline silicon wiring layer. Contact holes are formed in the insulating layer on the impurity diffusion region and on the drain region, and a conductive layer lies within the contact holes to connect the impurity diffusion regions to the polycrystalline silicon wiring layer. Further, a power source line and other wiring layers are provided on an isolation region between the transistors.
Inventors
- 👤 Yoshihisa Shiotari
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:05
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/858; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
341 words
A CMOS device comprising: a semiconductor substrate of a first conductivity type; a first transistor having a source region and a drain region of a second conductivity type formed in said semiconductor substrate spaced apart from one another, and having an insulation gate layer formed over said substrate between said source and drain regions; a well region of said second conductivity type provided in said semiconductor substrate; a second transistor having a source region and a drain region of said first conductivity type formed in said well region spaced apart from one another and having an insulation gate layer formed over said well region between said source and drain regions and extending to said insulation gate layer of said first transistor to thereby form a first insulation layer, said source and drain regions of said first and second transistors being separated from one another by a portion of said substrate and by a portion of said well region which forms an isolation region between said transistors; a first wiring layer positioned on said first insulating layer to cross said isolation region and to form gate electrodes of said first and second transistors; a second wiring layer crossing said isolation region and electrically connected the drain regions of said first and second transistors; a second insulating layer formed on said semiconductor substrate and on said well region for preventing said second wiring layer from directly contacting either said semiconductor substrate or said well region; a first electrical contact electrically connecting the drain region of said first transistor with said second wiring layer; a second electrical contact electrically connecting the drain region of said second transistor with said second wiring layer and having a structure the same as the structure of said first electrical contact; a third insulating layer disposed over at least those portions of said first and second wiring layers which are located over said isolation region; and a power source wiring layer disposed over said isolation region so as to cross said first and second wiring layers at right angles.
Claim 2
Dependent Claim
341 words
A CMOS device comprising: a semiconductor substrate of a first conductivity type; a first transistor having a source region and a drain region of a second conductivity type formed in said semiconductor substrate spaced apart from one another, and having an insulation gate layer formed over said substrate between said source and drain regions; a well region of said second conductivity type provided in said semiconductor substrate; a second transistor having a source region and a drain region of said first conductivity type formed in said well region spaced apart from one another and having an insulation gate layer formed over said well region between said source and drain regions and extending to said insulation gate layer of said first transistor to thereby form a first insulation layer, said source and drain regions of said first and second transistors being separated from one another by a portion of said substrate and by a portion of said well region which forms an isolation region between said transistors; a first wiring layer positioned on said first insulating layer to cross said isolation region and to form gate electrodes of said first and second transistors; a second wiring layer crossing said isolation region and electrically connected the drain regions of said first and second transistors; a second insulating layer formed on said semiconductor substrate and on said well region for preventing said second wiring layer from directly contacting either said semiconductor substrate or said well region; a first electrical contact electrically connecting the drain region of said first transistor with said second wiring layer; a second electrical contact electrically connecting the drain region of said second transistor with said second wiring layer and having a structure the same as the structure of said first electrical contact; a third insulating layer disposed over at least those portions of said first and second wiring layers which are located over said isolation region; and a power source wiring layer disposed over said isolation region so as to cross said first and second wiring layers at right angles.
Claim 3
Dependent Claim
122 words
A CMOS device according to claim 1, wherein each of said first and second electrical contacts comprises an impurity diffusion region having the same conductivity type as said drain region and being located in said semiconductor substrate and well region surfaces, respectively, contiguous with said respective drain regions, lying, at least in part, below said second wiring layers and electrically isolated from said second wiring layers by said second insulating layer; a contact hole formed in said second insulating layer over said impurity diffusion regions and said drain regions of each said transistor; and a conductive layer in each contact hole, said second wiring layer being electrically connected by said conductive layer and said impurity diffusions regions to said respective drain regions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-06-10 | 1988-12-10 | 1989-06-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-06-10 | 1992-12-10 | 1993-06-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-06-10 | 1996-12-10 | 1997-06-11 | $7700.00 | Window Closed / Lapsed |