Distributed arithmetic oversampling recursive digital filter

Claim 1

A distributed arithmetic oversampling recursive digital filter, comprising: (a) a recursive part of order q comprising a parallel loading register having an output terminal and an input terminal, and q-1 series registers each of r cells, r being an integer connected in cascade; (b) a non-recursive part of order p comprising series registers each of r cells each series register having one input terminal receiving input signals, said input signals being blockable P times out of N, wherein P and N are integers; (c) a modulo N counter with α output terminals; (d) a memory divided into N memory blocks, each of said memory blocks containing a set of calculated quantities characterizing the filtering to be carried out, said memory having α addressing input terminals corresponding to said blocks, said addressing input terminals being connected to said α outputs of said modulo N counter and said addressing input terminals within a block being connected to the output terminals of said series registers of said recursive and said non-recursive parts and said memory having an output terminal; (e) an adder-subtracter having an input terminal connected to the output terminal of said memory and having an output terminal; (f) an accumulator register having an input terminal connected to said output terminal of said adder-subtracter and having an output terminal connected to said input terminal of said parallel loading register and to said input terminal of said adder-subtracter; (g) a clock having a first output terminal connected to said parallel loading register and said series registers, said first output terminal delivering a clock signal at a frequency rf s , and a second output terminal connected to said modulo N counter, said second output terminal delivering a clock signal at a frequency f s , said filter having an input terminal for receiving samples at a sampling frequency f E , said frequency f s of said clock being equal to Nf E , said non-recursive part comprising at most K+1 series registers, K being an integer defined by the relationship (K-1) N+2.sup.α -N≦p+P-1<KN+2.sup.α -N, and wherein said filter further comprises a first plurality of first through Kth multiplexers each having first and second input terminals, a control input terminal and an output terminal, said output terminal of each said multiplexer being operatively connected to either said first or second input terminals according to a signal supplied to said control input signal, said second input terminal of each of said multiplexers being connected to the output terminal of an associated one of said series registers, said first input terminal of the jth multiplexer, j being an integer, 1<j≦K, being connected to the output terminal of that one of said series registers associated with the (j-1)-th multiplexer said first input terminal of said first multiplexer being connected to said input of said filter, and said control input terminal of said j-th multiplexer being controlled by said modulo N counter in such a way that when the content of said modulo N counter is at a maximum, said output terminal of said j-th multiplexer is operatively connected to said first input terminal of said j-th multiplexer, thereby making said series registers circulating, and when the content of said modulo N counter differs from its maximum output, said output terminal of said j-th multiplexer, is operatively connected to said second input terminal.