Patent US4520440A successfully refreshed from Google Patents.
US4520440A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Test verification of processor architecture having a partial instruction set
Assignee: International Business Machines Corp
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Filing: 1982-12-15
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Granted: 1985-05-28
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Expires: 2002-12-15
Abstract
Abstract A method for verifying the architectural integrity of a newly written or modified instruction set in a limited operating environment is described. More particularly, this methodology is adapted to perform such verification even though the processor under test has only a one or a few instructions in its partially complete instruction set. Such verification is accomplished using a minimum test driver, under control of a test processor, which loads the data necessary to execute the instruction being tested. The test system also provides actual or simulated I/O capabilities. After execution of that instruction, the test driver directs capture of the execution results for appropriate use. As an aid in performing the verification test, the test driver is provided with an invalid command that forces return of control to the test processor. In operation, the processor to be microcoded is tested instruction by instruction, via shared memory, with microcode corrections being made on the same basis to avoid error propagation into the remainder of the instruction set as it is developed.
Inventors
- 👤 Joseph P. Buonomo
- 👤 Wendell L. Perry
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 19:00
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
237 words
A method for verifying the architectural integrity of a processor under test having a limited instruction set, said method comprising the steps of: (a) providing a test support processor connected to communicate with the processor under test; (b) providing input/output support, including at least the capability for a display terminal, a printer and a disk drive, connected to said test support processor for use in association with said processor under test; (c) providing a minimally sized test control program to read test cases and initialize memory with data for an instruction to be tested, said test control program initializing the registers of said processor under test; (d) providing storage means, connected between said processor under test and said test processor, that is accessible and is to be shared by both of the processors; (e) loading said test control program into said shared memory and loading data sufficient to test one of the instructions of said limited instruction set of said processor under test into said shared memory, said test control program initiating execution of said one of the instructions by initiating execution of said data loaded into said shared memory; (f) passing verification test control to said processor under test to thereby cause execution of said instruction thereof; and thereafter (g) said test control program capturing and storing the results of execution of said instruction in said shared memory for subsequent inspection and comparison to desired results.
Claim 2
Independent Claim
237 words
A method for verifying the architectural integrity of a processor under test having a limited instruction set, said method comprising the steps of: (a) providing a test support processor connected to communicate with the processor under test; (b) providing input/output support, including at least the capability for a display terminal, a printer and a disk drive, connected to said test support processor for use in association with said processor under test; (c) providing a minimally sized test control program to read test cases and initialize memory with data for an instruction to be tested, said test control program initializing the registers of said processor under test; (d) providing storage means, connected between said processor under test and said test processor, that is accessible and is to be shared by both of the processors; (e) loading said test control program into said shared memory and loading data sufficient to test one of the instructions of said limited instruction set of said processor under test into said shared memory, said test control program initiating execution of said one of the instructions by initiating execution of said data loaded into said shared memory; (f) passing verification test control to said processor under test to thereby cause execution of said instruction thereof; and thereafter (g) said test control program capturing and storing the results of execution of said instruction in said shared memory for subsequent inspection and comparison to desired results.
Claim 3
Dependent Claim
33 words
The method according to claim 1 which comprises the additional step of passing control of said verification test back to said test processor after execution of the instruction being verified has been completed.
Claim 4
Dependent Claim
44 words
The method according to claim 2 wherein the passing of control of said verification test back to said test processor is accomplished by imbedding an invalid command in said test control program which, when encountered, forces a return of control to said test processor.
Claim 5
Dependent Claim
20 words
The method according to claim 1 wherein said input/output support is provided by having said test processor simulate the same.
Claim 6
Dependent Claim
33 words
The method according to claim 4 which comprises the additional step of passing control of said verification test back to said test processor after execution of the instruction being verified has been completed.
Claim 7
Dependent Claim
44 words
The method according to claim 5 wherein the passing of control of said verification test back to said test processor is accomplished by imbedding an invalid command in said test control program which, when encountered, forces a return of control to said test processor.
Claim 8
Independent Claim
174 words
A method of testing the hardware and the microcode associated with a processor under test, comprising the steps of: loading a minimally sized test control program into a memory, said test control program functioning to set up a test environment which may be used in association with the testing of the execution of any one of a plurality of instructions of said processor under test; loading a specific test case program into said memory, said test case program including data and instructions associated with the test of a specific one of said plurality of instructions of said processor under test, the test control program and the specific test case program constituting a composite program; executing said composite program, said processor under test performing the executing step, thereby producing a set of actual results; comparing the set of actual results with a set of theoretical, correct results thereby producing a set of discrepancies, said discrepancies being used to analyze and correct any errors associated with the hardware or the microcode of the processor under test.
Claim 9
Independent Claim
174 words
A method of testing the hardware and the microcode associated with a processor under test, comprising the steps of: loading a minimally sized test control program into a memory, said test control program functioning to set up a test environment which may be used in association with the testing of the execution of any one of a plurality of instructions of said processor under test; loading a specific test case program into said memory, said test case program including data and instructions associated with the test of a specific one of said plurality of instructions of said processor under test, the test control program and the specific test case program constituting a composite program; executing said composite program, said processor under test performing the executing step, thereby producing a set of actual results; comparing the set of actual results with a set of theoretical, correct results thereby producing a set of discrepancies, said discrepancies being used to analyze and correct any errors associated with the hardware or the microcode of the processor under test.
Claim 10
Dependent Claim
27 words
The method of claim 7, wherein said test control program: initializes the registers of said processor under test, and initiates execution of said specific test case program.
Claim 11
Dependent Claim
56 words
The method of claim 8, wherein: said specific test case program loads said data into said registers of said processor under test, the processor under test executing said instructions associated with the test of a specific one of said plurality of instructions using said data stored in said registers thereby yielding said set of actual results.
Claim 12
Dependent Claim
43 words
The method of claim 9, wherein said test control program stores said set of actual results in said memory, said set of actual results being compared with said set of theoretical, correct results via said comparing step thereby producing said set of discrepancies.
Claim 13
Dependent Claim
55 words
The method of claim 10, wherein said test control program and said test case program are loaded into said memory from an input/output support means by a test support processor, said test support processor performing said comparing step using said set of actual results stored in said memory and said set of theoretical, correct results.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-05-27 | 1988-11-26 | 1989-05-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-05-27 | 1992-11-26 | 1993-05-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-05-27 | 1996-11-26 | 1997-05-28 | $7700.00 | Window Closed / Lapsed |