Symmetry type loop communication system

Claim 2

A symmetric type loop communication system comprising a loop communication path, and a plurality of communication controlling stations connected in series by said loop communication path, each communication controlling station having means including a delay circuit connected to receive signals from said loop communication path and apply said signals to said communication path for performing a serial delay on said loop communication path of a bit serial transmission signal carried on said communication path from one station to another, an auxiliary input forming circuit for generating a transmission-right signal to be applied as a bit serial transmission signal on said loop communication path, and control circuit means connected to receive signals from said loop communication path for controlling the operation of said auxiliary input forming circuit to selectively apply said transmission-right signal from said auxiliary input forming circuit to said loop communication path in the absence of receipt of a transmission-right signal from said loop communication path.

Claim 3

A symmetric type loop communication system according to claim 1, in which said control circuit means in each of said plural communication controlling stations includes timer means for producing an output at the expiration of a set time which is different from the set time of each other control station; means connected to receive signals from said loop communication path for resetting said timer means of a station when a transmission-right signal from another control station is received from said loop communication path; and means for enabling said auxiliary input forming circuit to apply to said loop communication path said transmission-right signal together with message data in response to the output of said timer means.

Claim 4

A symmetric type loop communication system according to claim 2, further including selector means in each communication controlling station for selectively connecting either the output of said delay circuit or the output of said auxiliary input forming circuit to said control circuit means in response to a selection signal from said control circuit means.

Claim 5

A symmetric type loop communication system according to claim 3, further including a bypass circuit connected to said loop communication path in each communication controlling station for applying signals from said loop communication path directly to said selector means, said selector means being responsive to said selection signal for applying to said control means one of the outputs of said auxiliary input forming circuit, said delay circuit and said bypass circuit.

Claim 6

A symmetric type loop communication system according to claim 4, wherein said control circuit means further includes means responsive to the output of said timer means for generating a selection signal to control said selector to connect the outputs of said auxiliary input forming circuit and said delay circuit to said control circuit means, means for applying said transmission-right signal and message data to said loop communication path, and means for resetting said timer means and controlling said selector means to connect said bypass circuit to said control circuit means when a transmission-right signal is received in said control circuit means.

Claim 7

A symmetric type loop communication system according to claim 1, in which said delay circuit is a shift register having at least 4-bits delay.

Claim 8

A symmetric type loop communication system having a plurality of communication controlling stations connected to a loop communication path in series, each of said communication controlling stations comprising a delay circuit coupled to an input side terminal of each of said communication controlling stations for providing a delay time of the transmission of a received transmission-right signal depending on the bit length of said transmission-right signal to be circulated through said communication path, an auxiliary input forming circuit for generating a transmission-right signal, and a circuit means for outputting said transmissin-right signal from said delay circuit into an output side terminal of each of said communication controlling stations when said transmission-right signal is received from said communication path within a predetermined time interval and outputting said transmission-right signal from said auxiliary input forming circuit together with message data in each of said communication controlling stations into said output side terminal thereof when said transmission-right signal is not received from said communication path within said predetermined time interval.

Claim 9

A symmetric type loop communication system having a plurality of communication controlling stations connected to a loop communication path in series, each of said communication controlling stations comprising a delay circuit coupled to an input side terminal of each of said communication controlling stations for providing a delay time of the transmission of a received transmission-right signal depending on the bit length of said transmission-right signal to be circulated through said communication path, an auxiliary input forming circuit for generating a transmission-right signal, and a circuit means for outputting said transmissin-right signal from said delay circuit into an output side terminal of each of said communication controlling stations when said transmission-right signal is received from said communication path within a predetermined time interval and outputting said transmission-right signal from said auxiliary input forming circuit together with message data in each of said communication controlling stations into said output side terminal thereof when said transmission-right signal is not received from said communication path within said predetermined time interval.

Claim 10

A symmetric type loop communication system according to claim 7, in which each of said plural communication controlling stations further includes timer means which is reset when a transmission-right signal is received from said loop communication path for counting said preset time interval.

Claim 11

A symmetric type loop communication system according to claim 7, in which said delay circuit is a shift register having more than 4 bits.

Claim 12

A symmetric type loop communication system according to claim 7, each of said stations further comprising means for selectively bypassing said delay circuit.

Claim 13

A symmetric type loop communication system according to claim 10, in which each of said plural communication controlling stations has timer means with a set time different from each set time of the other control stations.

Claim 14

A symmetric type loop communication system according to claim 10, in which said delay circuit is a shift register having more than 4 bits.