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US3919484A Expired / Lapsed US ⏱️ 0.0 years remaining

Loop controller for a loop data communications system

Assignee: RCA Corp
•
Filing: 1974-03-01
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Granted: 1975-11-11
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Expires: 1994-03-01
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Abstract

Abstract A loop controller for a time division multiplexed loop communications system. The loop controller is connected in series with a plurality of data processors in a loop configuration. The loop controller provides a certain number of time slots in a frame. The data processors communicate with each other in channels comprising two time slots. Each data processor must acquire the same channel in each frame. The loop controller provides an adaptive delay function such that the total delay around the loop is a multiple of the time slots forming a frame to insure that the data processors acquire the same channel in each frame. In addition, the loop controller re-times the signals circulating on the loop and detects and counts violations of the modulation rule utilized by the signals circulating on the loop.

Inventors

  • 👤 Nicholas Frank Maxemchuk

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 18:49
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/20; H04L25/24; H04L25/242; H04L12/00; H04L12/28; H04L12/42; H04L12/422

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 365 words
In a time division multiplexed loop communications system having a plurality of data processors connected in series relation forming a loop, a loop controller connected in said loop and in series with said data processors, said loop controller comprising: means adapted for receiving and demodulating signals received from said loop; means couples to said receiving and demodulating means for extracting timing information signals from said signals received from said loop; timing means for providing transmit timing signals, synchronization signals and framing information signals; means responsive to said extracted timing information signals and to said transmit timing signals for retiming said demodulating signals with transmit signal timing information; a signal delay means for imparting an adjustable delay time to said retimed demodulating signals, said signal delay means comprising first and second shift registers, said first shift register being adapted to receive said retimed demodulated signals, said second shift register being adapted to receive marker signals at times corresponding to said first shift register receiving said retimed demodulating signals, said first shift register further being adapted to receive a spacer signal after receiving said retimed demodulated signals, said second shift register being adapted to receive a spacer indication signal at times corresponding to the receiving of a spacer signal by said first shift register, the delay provided by said signal delay means being related to the total number of spacer indication signals stored in said second shift register; a frame comparison means for comparing framing information from the signals provided by said delay means with the framing information signals from said timing means and for providing a search signal to said delay means based on the results of said comprison; means for coupling said search signal to said signal delay means; means for altering the total number of said spacer indication signals in said second shift register in response to said search signal for adjusting the delay time provided by said signal delay means; means for multiplexing the delayed signals from said delay means with said framing and synchronization signals from said timing means; and means for modulating said multiplexed signals in accordance with a particular modulation rule and for transmitting said modulated signals on said loop.
Claim 2
Dependent Claim 365 words
In a time division multiplexed loop communications system having a plurality of data processors connected in series relation forming a loop, a loop controller connected in said loop and in series with said data processors, said loop controller comprising: means adapted for receiving and demodulating signals received from said loop; means couples to said receiving and demodulating means for extracting timing information signals from said signals received from said loop; timing means for providing transmit timing signals, synchronization signals and framing information signals; means responsive to said extracted timing information signals and to said transmit timing signals for retiming said demodulating signals with transmit signal timing information; a signal delay means for imparting an adjustable delay time to said retimed demodulating signals, said signal delay means comprising first and second shift registers, said first shift register being adapted to receive said retimed demodulated signals, said second shift register being adapted to receive marker signals at times corresponding to said first shift register receiving said retimed demodulating signals, said first shift register further being adapted to receive a spacer signal after receiving said retimed demodulated signals, said second shift register being adapted to receive a spacer indication signal at times corresponding to the receiving of a spacer signal by said first shift register, the delay provided by said signal delay means being related to the total number of spacer indication signals stored in said second shift register; a frame comparison means for comparing framing information from the signals provided by said delay means with the framing information signals from said timing means and for providing a search signal to said delay means based on the results of said comprison; means for coupling said search signal to said signal delay means; means for altering the total number of said spacer indication signals in said second shift register in response to said search signal for adjusting the delay time provided by said signal delay means; means for multiplexing the delayed signals from said delay means with said framing and synchronization signals from said timing means; and means for modulating said multiplexed signals in accordance with a particular modulation rule and for transmitting said modulated signals on said loop.
Claim 3
Dependent Claim 60 words
The loop controller according to claim 1 wherein a certain number of time slots comprise one frame in said time division multiplexed communication system and wherein the time delay provided by said signal delay means is adjusted by said search signal such that the total time delay around the loop is a multiple of said certain number of time slots.
Claim 4
Dependent Claim 36 words
The loop controller according to claim 2 wherein said first and second shift registers each comprise a plurality of stages, said plurality of stages being equal to a multiple of said certain number of time slots.
Claim 5
Dependent Claim 33 words
The loop controller according to claim 3 further comprising means coupled to said means for receiving and demodulating said signals received from said loop, for detecting and counting errors in said modulation rule.
Claim 6
Dependent Claim 78 words
The loop controller according to claim 4 wherein said means for detecting and counting errors in said modulation rule comprises: means for analyzing said received demodulated signals coupLed to an error counter, said error counter being advanced by one for each modulation rule violation; and means for analyzing received demodulated synchroizing signals coupled to said error counter, said error counter being advanced by a number larger than one for violations of the modulation rule in the synchronizing signals.

References Cited (Backward Citations)

US3681759A Cited
US3692941A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-11-10 1979-05-12 1979-11-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-11-10 1983-05-12 1983-11-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-11-10 1987-05-12 1987-11-11 $7700.00 Window Closed / Lapsed

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