US4516248A
Expired / Lapsed
US
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Variable threshold receiver
Assignee: Raytheon Co
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Filing: 1983-01-21
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Granted: 1985-05-07
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Expires: 2003-01-21
Abstract
Abstract A variable threshold receiver is disclosed which compensates for direct current (dc) voltages present in a received signal. The receiver utilizes an integrator-comparator circuit to recover data which may have been distorted by the presence of dc voltages. The integrator-comparator circuit provides data recovery by tracking the average of the peak signal levels of the received signal, eliminating the need for a lengthy preamble to compensate for receiver attack time.
Inventors
- 👤 Thomas E. Barclay
- 👤 John A. Zett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 05:57
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/08; H03K5/082; H04; H04L; H04L12/00; H04L12/28; H04L12/40; H04L12/407; H04L12/413
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
242 words
Apparatus for decoding a composite signal having a varying d.c. offset voltage comprising: (a) an input transistor adapted to receive an input composite signal comprising discrete unipolar signals in varying sequence and amplitude and providing an output signal representative of said input signal at its emitter electrode; (b) a threshold transistor having it base electrode electrically connected to the emitter electrode's said input transistor; (c) a bias capacitor electrically connected between the emitter electrode of said threshold transistor and ground reference, the charging/discharging characteristics of said capacitor being related to the bandwidth of the composite signals so that the signal appearing at the emitter electrode of said threshold transistor is representative of the average peak amplitude levels in the composite signal; (d) a threshold bias transistor having its base electrically connected to the emitter of said threshold transistor; (e) a voltage divider network comprising a plurality of series-connected resistors, serially connected between the emitter electrode of said threshold bias transistor and ground; and (f) an integrator/cosmparator having two input terminals, one of said input terminals being electrically connected to the output signals of said input transistor and the other of said input terminals being electrically connected to a point between two of said plurality of resistors in said voltage divider network; whereby a decoded output signal is derived from said integrator/comparator by comparing the output signal obtained from said voltage divider with the signal obtained from the output of said input transistor.
Claim 2
Dependent Claim
242 words
Apparatus for decoding a composite signal having a varying d.c. offset voltage comprising: (a) an input transistor adapted to receive an input composite signal comprising discrete unipolar signals in varying sequence and amplitude and providing an output signal representative of said input signal at its emitter electrode; (b) a threshold transistor having it base electrode electrically connected to the emitter electrode's said input transistor; (c) a bias capacitor electrically connected between the emitter electrode of said threshold transistor and ground reference, the charging/discharging characteristics of said capacitor being related to the bandwidth of the composite signals so that the signal appearing at the emitter electrode of said threshold transistor is representative of the average peak amplitude levels in the composite signal; (d) a threshold bias transistor having its base electrically connected to the emitter of said threshold transistor; (e) a voltage divider network comprising a plurality of series-connected resistors, serially connected between the emitter electrode of said threshold bias transistor and ground; and (f) an integrator/cosmparator having two input terminals, one of said input terminals being electrically connected to the output signals of said input transistor and the other of said input terminals being electrically connected to a point between two of said plurality of resistors in said voltage divider network; whereby a decoded output signal is derived from said integrator/comparator by comparing the output signal obtained from said voltage divider with the signal obtained from the output of said input transistor.
Claim 3
Dependent Claim
29 words
The apparatus of claim 1 wherein said threshold bias transistor is responsive to an input signal to initiate a new signal average upon the new composite digital data signal.
Claim 4
Independent Claim
97 words
A method for generating a variable level threshold signal which averages the peak amplitude levels of the individual information signals in a composite signal having different, unipolar amplitude levels, comprising the steps of: (a) receiving the individual information signals; (b) determining the voltage level of the received individual information signals; (c) averaging within the duration of a bit time of an individual information signal the determined voltage level over a predetermined time period related to the bandwidth of the composite signal; and (d) producing a threshold level signal equal in amplitude to the averaged determined voltage level.
Claim 5
Independent Claim
97 words
A method for generating a variable level threshold signal which averages the peak amplitude levels of the individual information signals in a composite signal having different, unipolar amplitude levels, comprising the steps of: (a) receiving the individual information signals; (b) determining the voltage level of the received individual information signals; (c) averaging within the duration of a bit time of an individual information signal the determined voltage level over a predetermined time period related to the bandwidth of the composite signal; and (d) producing a threshold level signal equal in amplitude to the averaged determined voltage level.
Claim 6
Dependent Claim
144 words
Apparatus for generating a variable level threshold signal which averages the peak amplitude levels of the individual data signals in a composite signal having different, unipolar amplitude levels, comprising: (a) buffering means responsive to the application of a composite digital data signal to provide a high impedance to the transmission medium of the composite digital data signal; (b) means operatively connected to said buffering means for determining the voltage level of the individual digital data signals within the composite digital data signal; (c) means responsive of said determining means for averaging within the duration of a bit time of an individual information signal the determined voltage levels over a time period related to the bandwidth of the composite digital data signal; and (d) means responsive to said averaging means for producing a threshold bias level signal equal in amplitude to the averaged voltage level.
Claim 7
Dependent Claim
144 words
Apparatus for generating a variable level threshold signal which averages the peak amplitude levels of the individual data signals in a composite signal having different, unipolar amplitude levels, comprising: (a) buffering means responsive to the application of a composite digital data signal to provide a high impedance to the transmission medium of the composite digital data signal; (b) means operatively connected to said buffering means for determining the voltage level of the individual digital data signals within the composite digital data signal; (c) means responsive of said determining means for averaging within the duration of a bit time of an individual information signal the determined voltage levels over a time period related to the bandwidth of the composite digital data signal; and (d) means responsive to said averaging means for producing a threshold bias level signal equal in amplitude to the averaged voltage level.
Claim 8
Dependent Claim
30 words
The apparatus of claim 4 wherein said averaging means is responsive to an input signal to initiate a new average upon the receipt of a new composite digital data signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-05-06 | 1988-11-05 | 1989-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-05-06 | 1992-11-05 | 1993-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-05-06 | 1996-11-05 | 1997-05-07 | $7700.00 | Window Closed / Lapsed |