Fast-averaging noise-summing signal detector

Claim 2

A circuit for use in an automatic-frequency-scanning receiver in order to provide reliable signal lock-on capability in the presence of varying noise levels, said circuit comprising: means for dividing the receiver I-F output energy into two equal parts; a pair of detector networks each receiving an equal part of the I-F energy so divided; one of said networks including a first resistance-capacitance unit having a long time constant which is relatively short compared to the period of the receiver I-F output variations; the other of said networks including a second resistancecapacitance unit having a short time-constant which is short compared to that of the resistance-capacitance unit included in said one network; and means for applying the output of said one network to ''''correct'''' the output of said other network so as to minimize the effect of variations in the output noise level on the receiver''s signal lock-on capability.

Claim 3

A circuit for use in a signal receiver having an I-F amplifier section, said circuit comprising: means for dividing tHe signal output of said I-F amplifier section into two equal parts a first detector network receiving one part of the divided I-F signal a second detector network receiving the other part of the divided I-F signal a second detector network receiving the of the part of the divided I-F signal said first detector network including a long time constant circuit the period of which is short compared to the period of the receiver output level variations said second detector network including a short time constant circuit the period of which is short compared to that of the time constant circuit included in said first detector network a pair of d-c amplifiers respectively receiving the outputs of said two detector networks a differential amplifier to which the output of said first detector network is applied an auto level adjust circuit receiving the output of said differential amplifier a level shifter receiving the output of the d-c amplifier connected to said second detector network, and means for applying the output of said auto level adjust circuit to both detector networks and also to both d-c amplifiers, the auto level adjust circuit receiving level changes from said differential amplifier and converting these changes into a bias level for both the d-c amplifier connected to said first detector network and for the time constant circuit of such first detector network, the gain of the d-c amplifier connected to said first detector network being thus controlled to maintain the output level of said differential amplifier at zero, whereby the d-c amplifier connected to said second detector network remains at the zero logic level until a signal is detected by said receiver, whereupon the output level of such amplifier is driven to the positive level state.

Claim 4

A circuit for use in a signal receiver having an I-F amplifier section, said circuit comprising: means for dividing tHe signal output of said I-F amplifier section into two equal parts a first detector network receiving one part of the divided I-F signal a second detector network receiving the other part of the divided I-F signal a second detector network receiving the of the part of the divided I-F signal said first detector network including a long time constant circuit the period of which is short compared to the period of the receiver output level variations said second detector network including a short time constant circuit the period of which is short compared to that of the time constant circuit included in said first detector network a pair of d-c amplifiers respectively receiving the outputs of said two detector networks a differential amplifier to which the output of said first detector network is applied an auto level adjust circuit receiving the output of said differential amplifier a level shifter receiving the output of the d-c amplifier connected to said second detector network, and means for applying the output of said auto level adjust circuit to both detector networks and also to both d-c amplifiers, the auto level adjust circuit receiving level changes from said differential amplifier and converting these changes into a bias level for both the d-c amplifier connected to said first detector network and for the time constant circuit of such first detector network, the gain of the d-c amplifier connected to said first detector network being thus controlled to maintain the output level of said differential amplifier at zero, whereby the d-c amplifier connected to said second detector network remains at the zero logic level until a signal is detected by said receiver, whereupon the output level of such amplifier is driven to the positive level state.

Claim 5

The combination of claim 2 in which each of said detector networks includes a sample and hold circuit which acts to prevent change of time constants and d-c amplifier levels during periods of signal lock-on.

Claim 6

The combination of claim 3 further including a source of blanking pulses, and means for applying blanking pulses from said source to each of said detector networks to control the respective sample and hold circuits included therein.

Claim 7

The combination of claim 4, further including a source of reverence voltage, and means for applying a reference voltage from such source to said differential amplifier.

Claim 8

The combination of claim 5 further including a source of receiver stop-sweep control voltage, a first OR gate, and means for selectively applying to said first OR gate a receivers stop-sweep control voltage from said source and also the output of said level shifter.

Claim 9

The combination of claim 6, further including a second OR gate to which the output of said first OR gate is applied, said second OR gate acting to automatically control the application of blanking pulses to blank the receiver without stopping the sweep.

Claim 10

The combination of claim 7, further including means for selectively applying to said second OR gate a receiver blanking signal during periods between band changes or upon the reception of spurious energy variations.