Integrated program counter memory management register and incrementer

Claim 2

An integrated program counter, memory and incrementer cell comprising: program counter means; memory storage means; a first data bus means connected to said program counter means and said memory storage means for providing external access to said program counter means and said memory storage means; second data bus means connected to said program counter means and said memory storage means for providing access to said program counter means for reading and to said memory storage means for writing; sense means connected to said second data bus means for sensing a logic value of said program counter means on said second data bus means and maintaining said logic value on said second bus means; and increment means, connected to said second bus means and said program counter means and having an input increment terminal, for reading said logic value on said second data bus means and writing an incremented logic value in said program counter means when said program counter means is disconnected from said second data bus means in response to an increment signal on said increment signal input terminal.

Claim 3

An integrated cell according to claim 1 including means for interconnecting said program counter means and said second data bus means for reading only.

Claim 4

An integrated cell according to claim 1 including means for interconnecting said memory storage means and said second data bus means for writing only.

Claim 5

The integrated cell according to claim 3, wherein said interconnecting means includes a first and second switch means each having a first and second terminal and a control terminal, said first and second switch means having said first and second terminals connected in series between a logic value signal source and said memory storage means, said control terminal of said first switch means is connected to a write enable signal source, said control terminal of said second switch means is connected to said second data bus means for writing said signal source logic value in said memory storage means as a function of the logic value of said second data bus means.

Claim 6

An integrated cell according to claim 1 including means for connecting said program counter means to said first data bus means for reading and writing and means for connecting said memory storage means to said first data bus means for reading only.

Claim 7

An integrated cell according to claim 1 including a third data bus providing exterior access to said cell and means for interconnecting said program counter means and said third data bus for reading and writing.

Claim 8

An integrated cell according to claim 6 including means for interconnecting said program counter means and said first data bus means for reading only and means for interconnecting said memory storage means and said first data bus means for reading only.

Claim 9

The integrated cell according to claim 1, wherein said increment means includes an increment output terminal and means for providing an output increment signal on said increment output terminal when said increment means writes a logic low in said program counter means.

Claim 10

The integrated cell according to claim 8, wherein said output increment signal providing means includes a switch means connected between said increment input and output terminals and a control terminal connected to said second data bus means for activating said switch means to transmit an increment signal from said increment input terminal to said increment output terminal for a read logic high on said second data bus means.

Claim 11

An integrated register, memory and incrementer structure comprising: first data bus means for providing external access to said integrated structure; second data bus means for providing internal access to said integrated structure; register means controllably connected to said first and second data bus means; memory means controllably connected to said first and second data bus means; sense means connected to said second data bus means for sensing a logic value on said second data bus means; increment means connected to said second data bus means and said register means for incrementing said register means in response to an increment signal and said logic value of said second data bus means; and control means connected to said register, memory, sense and increment means for connecting said register means to said second bus means to read a logic value of said register means onto said second bus means, for activating said sense means to sense said logic value of said register means on said second bus means, for connecting said memory means to said second bus means to write said logic value on said second bus means into said memory means, for disconnecting said register means from said second bus means and for providing an increment input signal to said increment means.

Claim 12

An integrated register, memory and incrementer structure comprising: first data bus means for providing external access to said integrated structure; second data bus means for providing internal access to said integrated structure; register means controllably connected to said first and second data bus means; memory means controllably connected to said first and second data bus means; sense means connected to said second data bus means for sensing a logic value on said second data bus means; increment means connected to said second data bus means and said register means for incrementing said register means in response to an increment signal and said logic value of said second data bus means; and control means connected to said register, memory, sense and increment means for connecting said register means to said second bus means to read a logic value of said register means onto said second bus means, for activating said sense means to sense said logic value of said register means on said second bus means, for connecting said memory means to said second bus means to write said logic value on said second bus means into said memory means, for disconnecting said register means from said second bus means and for providing an increment input signal to said increment means.

Claim 13

In an integrated structure according to claim 10, wherein said control means control the interconnection of said register and memory means and said first data bus means to control external access thereto for reading and writing.

Claim 14

An integrated structure according to claim 10, wherein said increment means provides an output increment signal as a function of said increment input signal and said logic value on said second data bus means.

Claim 15

An integrated structure according to claim 10, wherein said control means maintains said sense means activated for a duration of a period when said memory means is connected to said second data bus means and a duration of said increment input signal so that said sense means maintains a pre-incremented logic value of said register means on said second bus means.