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Patent US4513343A successfully refreshed from Google Patents.
US4513343A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Short circuit protector having fold-back trip point for solid state switching device
Assignee: Eaton Corp
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Filing: 1982-12-27
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Granted: 1985-04-23
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Expires: 2002-12-27
Abstract
Abstract A transistor circuit (18) is series connected with a solid state switching device (14) and a load (4) controlled by that device (14) to protect that device (14) from overcurrents resulting from short circuits such as across the load (4). The transistor circuit (18) detects the overcurrent and switches to a high impedance state in response to that detection. The circuit (18) is self-resettable to restore to the low impedance state each half-cycle of applied voltage, thereby to automatically restore the switching device (14) to normal operation immediately upon removal of the short, and is set to initially respond to a level of current sufficiently high to preclude switching in response to inrush currents. Initial switching of the circuit (18) to its high impedance state latches a reduced level detection circuit (R1-R2-Q4) in the transistor circuitry (18) whereby the latter switches to its high impedance state upon detecting lower overcurrent values for each successive half-cycle until the short is removed. The predictability of the response range for the circuit, especially in the reduced level voltage detection mode, is improved by placing a resistor (R5) in series with the control switching transistor (Q3) for the circuit.
Inventors
- 👤 Lawrence J. Ryczek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 20:29
CPC Classifications
H; H02; H02H; H02H3/00; H02H3/08
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
174 words
An overcurrent protection circuit for limiting current flow to a solid state switching device connected in series with said circuit, a load controlled by said switching device, and a full wave rectified DC source, said circuit comprising, in combination: means rendering said circuit conductive in a low impedance state upon application of DC power to said circuit; first detection means for sensing current in said circuit and causing said circuit to switch to a high impedance state when said current exceeds a first predetermined value and for connecting a second detection means in said circuit, said second detection means being responsive to a second predetermined current value less than said first predetermined current value for causing said circuit to switch to said high impedance state; means switching said circuit to said low impedance state at the end of each half-cycle of DC power applied to said circuit; and capacitor means for maintaining said second detection means connected in said circuit for subsequent successive half-cycles until said current does not exceed said second predetermined value.
Claim 2
Dependent Claim
174 words
An overcurrent protection circuit for limiting current flow to a solid state switching device connected in series with said circuit, a load controlled by said switching device, and a full wave rectified DC source, said circuit comprising, in combination: means rendering said circuit conductive in a low impedance state upon application of DC power to said circuit; first detection means for sensing current in said circuit and causing said circuit to switch to a high impedance state when said current exceeds a first predetermined value and for connecting a second detection means in said circuit, said second detection means being responsive to a second predetermined current value less than said first predetermined current value for causing said circuit to switch to said high impedance state; means switching said circuit to said low impedance state at the end of each half-cycle of DC power applied to said circuit; and capacitor means for maintaining said second detection means connected in said circuit for subsequent successive half-cycles until said current does not exceed said second predetermined value.
Claim 3
Dependent Claim
260 words
An overcurrent protection circuit for limiting current flow to a solid state switching device connected in series with said circuit, a load controlled by said switching device, and a full wave rectified DC source, said circuit comprising, in combination: a pair of terminals; first transistor means connected across said terminals and driven into conduction upon the application of DC power to said terminals for switching said circuit to a low impedance state; means for sensing current in said circuit and for generating a voltage across said terminals proportionate to said current; first voltage detection means connected across said terminals; second voltage detection means and second transistor means connected in series across said terminals; third transistor means connected across said terminals; said second transistor means driven into conduction in response to a first predetermined voltage at said first voltage detection means for connecting said second voltage detection means into said circuit; said third transistor means driven into conduction in response to a second predetermined voltage less than said first predetermined voltage at said second voltage detection means for rendering said first transistor means non-conductive thereby switching said circuit to a high impedance state, said circuit switching to said low impedance state at the end of each half-cycle of DC power applied to said terminals; and capacitor means for maintaining said second transistor means conductive during subsequent successive half-cycles following said switching of said circuit to a high impedance state thereby to maintain said second voltage detection means connected in said circuit until said voltage does not reach said second predetermined value.
Claim 4
Dependent Claim
260 words
An overcurrent protection circuit for limiting current flow to a solid state switching device connected in series with said circuit, a load controlled by said switching device, and a full wave rectified DC source, said circuit comprising, in combination: a pair of terminals; first transistor means connected across said terminals and driven into conduction upon the application of DC power to said terminals for switching said circuit to a low impedance state; means for sensing current in said circuit and for generating a voltage across said terminals proportionate to said current; first voltage detection means connected across said terminals; second voltage detection means and second transistor means connected in series across said terminals; third transistor means connected across said terminals; said second transistor means driven into conduction in response to a first predetermined voltage at said first voltage detection means for connecting said second voltage detection means into said circuit; said third transistor means driven into conduction in response to a second predetermined voltage less than said first predetermined voltage at said second voltage detection means for rendering said first transistor means non-conductive thereby switching said circuit to a high impedance state, said circuit switching to said low impedance state at the end of each half-cycle of DC power applied to said terminals; and capacitor means for maintaining said second transistor means conductive during subsequent successive half-cycles following said switching of said circuit to a high impedance state thereby to maintain said second voltage detection means connected in said circuit until said voltage does not reach said second predetermined value.
Claim 5
Dependent Claim
47 words
The invention defined in claim 2 further comprising resistor means connected in series with said first transistor means for linearizing the early turn-on portion of said first transistor means, thereby to improve the predictability of the current level in said circuit corresponding to said second predetermined voltage.
Claim 6
Dependent Claim
24 words
The invention defined in claim 2 wherein said solid state switching device is a proximity limit switch operable to control an AC load device.
Claim 7
Dependent Claim
62 words
The invention defined in claim 1 wherein said means rendering said circuit conductive in a low impedance state comprises transistor means connected across said D.C. power, and further comprising resistor means connected in series with said transistor means across said D.C. power for linearizing the early turn-on portion of said transistor means, thereby to improve the predictability of said second current level.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-04-22 | 1988-10-22 | 1989-04-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-04-22 | 1992-10-22 | 1993-04-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-04-22 | 1996-10-22 | 1997-04-23 | $7700.00 | Window Closed / Lapsed |