Overload protection circuit

Claim 2

An overload protection circuit for limiting the current through a circuit to be protected, comprising: a transistor circuit having first and second transistor stages, full wave rectifier means connecting said transistor circuit to said circuit to be protected, biasing means in said transistor circuit for blocking conduction of said first transistor stage and driving said second transistor stage into conduction when bipolar current signals coupled to said full wave rectifier means from said circuit to be protected are below a predetermined amplitude, and for blocking said second transistor stage and for driving said first transistor state into conduction when bipolar signals coupled to said full wave rectifier means from said circuit to be protected exceed said predetermined amplitude, and load means in said first transistor stage for limiting the amount of current flowing in a circuit comprising said first transistor stage, said full wave rectifier means and said circuit to be protected to a value below said predetermined amplitude, when said first transistor stage is driven to conduction.

Claim 3

The overload protection circuit defined in claim 1 wherein said full wave rectifier means includes input terminals coupled to said circuit to be protected and output terminals coupled to said transistor circuit and wherein said first and second transistor stages each have conduction paths and said conduction paths of said first and second trAnsistor stages are connected in parallel, the parallel combination of said conduction paths of said first and second transistor stages being connected across said output terminals of said full wave rectifier means.

Claim 4

The overload protection circuit defined in claim 2 wherein said first transistor stage further comprises an input circuit connected to said biasing means such that the voltage output of said biasing means controls the operation of said first transistor stage, and said second transistor stage further comprises an input circuit connected to the output circuit of said first transistor stage in such a manner that the operation of said first transistor stage controls the operation of said second transistor stage.

Claim 5

The overload protection circuit defined in claim 3 wherein the output terminals of said overload protection circuit are connected across said full wave rectifier means, said rectifier means further comprising a capacitor connected across the input terminals.

Claim 6

The overload protection circuit defined in claim 1 wherein said full wave rectifier means is constructed in the form of a bridge rectifier.

Claim 7

An overload protection circuit for limiting the current flowing in a circuit to be protected, comprising: first and second input terminals, voltage divider means connected across said first and second input terminals, said voltage divider means having a tap, first and second transistors, each of said transistors having a control electrode and a conduction path, means connecting said control electrode of said first transistor to said tap of said voltage divider means, said conduction path of said first transistor being connected across said input terminals, load means connected in series with said conduction path of said first transistor, means connecting said control electrode of said second transistor to said conduction path of said first transistor and said load means so that the voltage developed across said load means by current flow through said conduction path of said first transistor controls the operation of said second transistor, the conduction path of said second transistor being connected across said input terminals, and full wave rectifier means connected between said input terminals and said circuit to be protected, the relative resistance values of said voltage divider and said load means being selected so that said first transistor is blocked and said second transistor conducts when the current flowing in said circuit to be protected is below a predetermined amplitude, and said second transistor is blocked and said first transistor is conducting when said current is flowing in said circuit to be protected exceeds said predetermined amplitude.

Claim 8

An overload protection circuit for limiting the current flowing in a circuit to be protected, comprising: first and second input terminals, voltage divider means connected across said first and second input terminals, said voltage divider means having a tap, first and second transistors, each of said transistors having a control electrode and a conduction path, means connecting said control electrode of said first transistor to said tap of said voltage divider means, said conduction path of said first transistor being connected across said input terminals, load means connected in series with said conduction path of said first transistor, means connecting said control electrode of said second transistor to said conduction path of said first transistor and said load means so that the voltage developed across said load means by current flow through said conduction path of said first transistor controls the operation of said second transistor, the conduction path of said second transistor being connected across said input terminals, and full wave rectifier means connected between said input terminals and said circuit to be protected, the relative resistance values of said voltage divider and said load means being selected so that said first transistor is blocked and said second transistor conducts when the current flowing in said circuit to be protected is below a predetermined amplitude, and said second transistor is blocked and said first transistor is conducting when said current is flowing in said circuit to be protected exceeds said predetermined amplitude.

Claim 9

The overload connections defined in claim 6 wherein said full wave rectifier means is constructed in the form of a bridge rectifier.

Claim 10

The overload connection circuit defined in claim 6 further comprising a capacitor connected across said full wave rectifier means and said circuit to be protected, said capacitor having a value such that the response time of said first and said second transistors to current signals having relatively steep leading edges in increased.