p-n Junction controlled field emitter array cathode

Claim 2

A field emitter array (FEA) comprising: a semiconductor substrate, an emitter surface formed on said substrate; a plurality of field emitter sites, with each field emitter site including an emitter pyramid, with a tip, sides, and a base for emitting electrons in the presence of an electric field, wherein the base of said emitter pyramid is disposed upon said emitter surface, said emitter site also including a permanent reverse-biased p-n junction, where said junction is the boundary between a p-type layer and an n-type layer of semiconductor material, wherein said p-n junction is positioned relative to said emitter pyramid so that an electron current flowing from said substrate into said emitter pyramid must traverse said p-n junction and wherein said p-n junction is oriented so that the n-layer is disposed between said junction and the tip of said emitter pyramid and is isolated from all other emitter pyramid n-layers, said p-n junction acting to limit the magnitude of the current density flowing therethrough to j sat , where j sat is the saturation current density of said p-n junction in reverse bias; and a grid, positioned above said emitter surface, for inducing the emission of electron current from said emitter pyramid where said grid is positively biased relative to said emitter pyramid with a bias voltage sufficient to cause said p-n junction to operate in reverse-biased saturation.

Claim 3

The FEA recited in claim 1, wherein all of said p-n junctions have equal area; and further comprising means for biasing said grid relative to said emitter pyramid with a reverse bias sufficient to cause said p-n junction to operate in reverse-biased saturation.

Claim 4

The FEA recited in claim 2, wherein said p-n junctions are disposed at the base of said pyramids.

Claim 5

The FEA recited in claim 3 wherein: said substrate is fabricated from a single-crystal silicon wafer and wherein: said emitter surface is a planar surface oriented parallel to the 100 plane of said silicon substrate.

Claim 6

The FEA recited in claim 4 wherein: the sides of said emitter pyramid are substantially parallel to the 111 planes of said silcon substrate.

Claim 7

The FEA recited in claim 5 wherein: said emitter pyramid is integral with said silicon substrate.

Claim 8

The FEA recited in claim 6 wherein: said p-n junction is substantially parallel to the 100 plane of said silicon substrate.

Claim 9

The FEA recited in claim 7 wherein: said p-n junction is disposed within said emitter pyramid.

Claim 10

The FEA recited in claim 8 wherein: the radii of the tip of said emitter pyramid is in the range of about 100 Angstroms to about 600 Angstroms.

Claim 11

The FEA recited in claim 9 wherein: the thickness of said grid is in the range of about 0.2 microns to about 1.5 microns.

Claim 12

An FEA comprising: a semiconductor substrate; an emitter surface formed on said substrate; a planar, permanent reverse-biased p-n junction disposed within said substrate parallel to said emitter surface, where said p-n junction is the boundary between a p-type layer and an n-type layer of semiconductor material, wherein said n-layer is disposed between said junction and said emitter surface and is isolated from all other emitter pyramid n-layers, said p-n junction for limiting the magnitude of the current density flowing there-through to j sat , where j sat is saturation current density of the reverse-biased junction; a plurality of isolation grooves formed in said emitter surface, wherein the bottom of said grooves is below said p-n junction; a plurality of isolation islands formed on said substrate, wherein each isolation island is circumscribed by said isolation grooves and wherein the area of each isolation island is substantially equal to a constant value, A p-n ; a plurality of emitter pyramids, each with a tip, sides, and a base, formed on said emitter surface wherein only one emitter pyramid is disposed on each isolation island so that the magnitude of the current emitted through the tip of each of said emitter pyramid is equal to: I=j.sub.sat ×A.sub.p-n a grid, positioned above said emitter surface, for inducing the emission of electron current from the tips of said emitter pyramids where said grid is positively biased relative to said emitter pyramids with a bias sufficient to cause said p-n junction to operate in reverse-biased saturation.

Claim 13

An FEA comprising: a semiconductor substrate; an emitter surface formed on said substrate; a planar, permanent reverse-biased p-n junction disposed within said substrate parallel to said emitter surface, where said p-n junction is the boundary between a p-type layer and an n-type layer of semiconductor material, wherein said n-layer is disposed between said junction and said emitter surface and is isolated from all other emitter pyramid n-layers, said p-n junction for limiting the magnitude of the current density flowing there-through to j sat , where j sat is saturation current density of the reverse-biased junction; a plurality of isolation grooves formed in said emitter surface, wherein the bottom of said grooves is below said p-n junction; a plurality of isolation islands formed on said substrate, wherein each isolation island is circumscribed by said isolation grooves and wherein the area of each isolation island is substantially equal to a constant value, A p-n ; a plurality of emitter pyramids, each with a tip, sides, and a base, formed on said emitter surface wherein only one emitter pyramid is disposed on each isolation island so that the magnitude of the current emitted through the tip of each of said emitter pyramid is equal to: I=j.sub.sat ×A.sub.p-n a grid, positioned above said emitter surface, for inducing the emission of electron current from the tips of said emitter pyramids where said grid is positively biased relative to said emitter pyramids with a bias sufficient to cause said p-n junction to operate in reverse-biased saturation.

Claim 14

The FEA recited in claim 11 wherein: said substrate is fabricated from a single crystal silcon wafer and wherein: said emitter surface is a planar surface oriented parallel to the 100 plane of said silicon substrate.

Claim 15

The FEA recited in claim 12 wherein: the side of said emitter pyramids are substantially parallel to the 111 planes of said substrate.

Claim 16

The FEA recited in claim 13 wherein: said emitter pyramids are integral with said silicon substrate.

Claim 17

An FEA comprising: a substrate formed from a single crystal silicon wafer; a planar emitter surface formed on said substrate where said emitter surface is parallel to the 100 plane of said substrate; a plurality of emitter pyramids formed on said emitter surface for emitting an electron current, each of said emitter pyramids including a p-type layer and an n-type layer with a planar reverse-biased p-n junction disposed therebetween, wherein said n-layer is isolated from all other emitter pyramid n-layers, said p-n junction being disposed parallel to said emitter surface and completely spanning the cross-section of the emitter pyramid so that an electron current flowing from the substrate to the tip must pass through the reverse-biased p-n junction and so that the magnitude of said electron current is equal to the saturation current density of said p-n junction multiplied by the area of said p-n junction; and a grid, disposed above the emitter surface, biased positively relative to said emitter pyramids with a bias voltage sufficient to cause said p-n junction to operate in reverse-biased saturation, said grid for inducing the emission of electron current from said emitter pyramids.

Claim 18

An FEA comprising: a substrate formed from a single crystal silicon wafer; a planar emitter surface formed on said substrate where said emitter surface is parallel to the 100 plane of said substrate; a plurality of emitter pyramids formed on said emitter surface for emitting an electron current, each of said emitter pyramids including a p-type layer and an n-type layer with a planar reverse-biased p-n junction disposed therebetween, wherein said n-layer is isolated from all other emitter pyramid n-layers, said p-n junction being disposed parallel to said emitter surface and completely spanning the cross-section of the emitter pyramid so that an electron current flowing from the substrate to the tip must pass through the reverse-biased p-n junction and so that the magnitude of said electron current is equal to the saturation current density of said p-n junction multiplied by the area of said p-n junction; and a grid, disposed above the emitter surface, biased positively relative to said emitter pyramids with a bias voltage sufficient to cause said p-n junction to operate in reverse-biased saturation, said grid for inducing the emission of electron current from said emitter pyramids.