US4512018A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Shifter circuit
Assignee: Unisys Corp
•
Filing: 1983-03-08
•
Granted: 1985-04-16
•
Expires: 2003-03-08
Abstract
Abstract A new and improved shifter circuit for multiplexing bytes of data into various orders on a finite size bus is disclosed. The improved shifter circuit includes an array of barrel shifter circuits arranged into N groups of M shifter circuits per group wherein each shifter circuit has P data input terminals and P output terminals. The letters N, M and P represent integers. Each of the P output terminals of each of the M shifter circuits in a group are coupled to one another, respectively, so as to form N×P output terminals of the array.
Inventors
- 👤 Andrew E. Phelps
- 👤 Allen Ta-Ming Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 11:44
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/76; G06F5/00; G06F5/01; G06F5/015
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
186 words
An array of shifter circuits arranged into N groups of M shifter circuits per group wherein both N and M are integers greater than one, each shifter circuit has P data input terminals, P control input terminals and P output terminals, where P is a positive integer, each of said P output terminals of the M shifter circuits in a group being coupled to one another, respectively, so as to form N×P output terminals of said array; each of said shifter circuits comprising P columns by P rows of transistor switching means, each having an input and an output element and a control element wherein the control element of each switching means in a row is coupled to corresponding ones of the control input terminals, the input element of each of the transistor switching means in a column being coupled to corresponding ones of the data input terminals and the output element of each of the transistor switching means in a row being coupled to respective ones of said output terminals shifted in position as a function of control signals supplied on said control input terminals.
Claim 2
Dependent Claim
186 words
An array of shifter circuits arranged into N groups of M shifter circuits per group wherein both N and M are integers greater than one, each shifter circuit has P data input terminals, P control input terminals and P output terminals, where P is a positive integer, each of said P output terminals of the M shifter circuits in a group being coupled to one another, respectively, so as to form N×P output terminals of said array; each of said shifter circuits comprising P columns by P rows of transistor switching means, each having an input and an output element and a control element wherein the control element of each switching means in a row is coupled to corresponding ones of the control input terminals, the input element of each of the transistor switching means in a column being coupled to corresponding ones of the data input terminals and the output element of each of the transistor switching means in a row being coupled to respective ones of said output terminals shifted in position as a function of control signals supplied on said control input terminals.
Claim 3
Dependent Claim
16 words
An array as in claim 1 wherein each of said transistor switching means is an MOSFET.
Claim 4
Dependent Claim
18 words
An array as in claim 1 wherein each of said transistor switching means is a pair of MOSFETs.
Claim 5
Dependent Claim
31 words
An array as in claim 1 wherein N is equal to eight, M is equal to four and P is equal to four such that said array is a 128-to-32 shifter.
Claim 6
Dependent Claim
23 words
An array as in claim 1 wherein N is equal to eight, M is equal to one and P is equal to four.
Claim 7
Dependent Claim
180 words
An array of barrel shifter circuits arranged into N groups of M shifter circuits per group wherein each barrel shifter circuit has P data input terminals, P control input terminals and P output terminals, N, M and P are integers, each of said output terminals of the barrel shifter circuits in a group being coupled to one another, respectively, so as to form N×P output terminals of said array, wherein each of said barrel shifter circuits comprises P columns by P rows of transistor switching means, each having an input and an output element and a control element wherein the control element of each switching means in a row is coupled to corresponding ones of the control input terminals, the input element of each of the transistor switching means in a column being coupled to corresponding ones of the data input terminals and the output element of each of the transistor switching means in a row being coupled to respective ones of said output terminals shifted in position as a function of control signals supplied on said control input terminals.
Claim 8
Dependent Claim
180 words
An array of barrel shifter circuits arranged into N groups of M shifter circuits per group wherein each barrel shifter circuit has P data input terminals, P control input terminals and P output terminals, N, M and P are integers, each of said output terminals of the barrel shifter circuits in a group being coupled to one another, respectively, so as to form N×P output terminals of said array, wherein each of said barrel shifter circuits comprises P columns by P rows of transistor switching means, each having an input and an output element and a control element wherein the control element of each switching means in a row is coupled to corresponding ones of the control input terminals, the input element of each of the transistor switching means in a column being coupled to corresponding ones of the data input terminals and the output element of each of the transistor switching means in a row being coupled to respective ones of said output terminals shifted in position as a function of control signals supplied on said control input terminals.
Claim 9
Dependent Claim
106 words
In a circuit arrangement for multiplexing bytes of data into various orders of arrangements of the bytes, an array of barrel shifter circuits arranged into N groups of M shifter circuits per group where N and M are both integers greater than one; and each barrel shifter circuit is disposed for receiving P data input signals and P control input signals and for providing P output signals on P output terminals, wherein P is a positive integer, each of said output terminals of the barrel shifter circuits in a group being coupled to one another, respectively, so as to form N×P output terminals of said array.
Claim 10
Dependent Claim
106 words
In a circuit arrangement for multiplexing bytes of data into various orders of arrangements of the bytes, an array of barrel shifter circuits arranged into N groups of M shifter circuits per group where N and M are both integers greater than one; and each barrel shifter circuit is disposed for receiving P data input signals and P control input signals and for providing P output signals on P output terminals, wherein P is a positive integer, each of said output terminals of the barrel shifter circuits in a group being coupled to one another, respectively, so as to form N×P output terminals of said array.
Claim 11
Dependent Claim
116 words
An array as in claim 7 wherein each of said shifter circuits comprises P columns by P rows of transistor switching means, each having an input and an output element and a control element wherein the control element of each switching means in a row is coupled to corresponding ones of the control input terminals, the input element of each of the transistor switching means in a column being coupled to corresponding ones of the data input terminals and the output element of each of the transistor switching means in a row being coupled to respective ones of said output terminals shifted in position as a function of control signals supplied on said control input terminals.
Claim 12
Dependent Claim
16 words
An array as in claim 8 wherein each of said transistor switching means is an MOSFET.
Claim 13
Dependent Claim
18 words
An array as in claim 8 wherein each of said transistor switching means is a pair of MOSFETs.
Claim 14
Dependent Claim
31 words
An array as in claim 8 wherein N is equal to eight, M is equal to four and P is equal to four such that said array is a 128-to-32 shifter.
Claim 15
Dependent Claim
23 words
An array as in claim 8 wherein N is equal to eight, M is equal to one and P is equal to four.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-04-15 | 1988-10-15 | 1989-04-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-04-15 | 1992-10-15 | 1993-04-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-04-15 | 1996-10-15 | 1997-04-16 | $7700.00 | Window Closed / Lapsed |