US4157458A
Expired / Lapsed
US
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Circuit for use either as a serial-parallel converter and multiplexer or a parallel-serial converter and demultiplexer in digital transmission systems
Assignee: Individual
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Filing: 1977-12-14
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Granted: 1979-06-05
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Expires: 1997-12-14
Abstract
Abstract A serial-parallel converter converts serial mode 8-bit words, delivered from a plurality of primary digital multiplx highways into parallel mode 8-bit words and multiplexes the 8-bit words to form a signal for a supermultiplex highway. The converter comprises eight parallel-write, serial-read input shift registers and seven serial-write, serial-read output shift registers. The write inputs of the output shift registers are respectively connected to the serial output of the input shift registers having the same rank. The serial read outputs of the output shift registers deliver a serial output of the eighth input shift register to the supermultiplex highway. All of the input shift registers comprise eight stages. The output shift registers have decreasing numbers of stages from 7 down to 1. The writing operation, into input shift registers, and shifting operation through all registers are controlled by a single 8-stage shift register. That single shift register circuit may also be used for demultiplexing the signals on a supermultiplex highway and converting the resulting parallel-mode 8-bit words into serial-mode 8-bit words to be delivered to outgoing primary digital multiplex highways. That single shift register circuit is particularly well-suited for time division switching systems.
Inventors
- 👤 Alain Y. D. Roche
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 10:53
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04J; H04J3/00; H04J3/02; H04J3/08; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/45
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
309 words
A converter circuit for a PCM switching system, means for connecting up to a predetermined number of primary digital multiplex highways with synchronized time frames and bit rates to said converter circuit, said converter comprising means for converting primary multiplex highway channel data from a serial mode into a parallel mode, means for multiplexing said parallel mode channel data to form a supermultiplex highway of signals, means for providing a plurality of cyclically recurring time slots with as many parallel mode channels as there are primary digital multiplex highway connections on said converter circuit, said channel data being arranged in n-bit words, m-1 serial-write, serial-read output shift register means in said converter circuit, each of said m-1 shift register means having one stage less than the number of stages in the preceding shift register means, m parallel-write serial-read input shift register means for receiving signals from individually associated ones of said primary highways, each of said input shift register means having n-stages, means for connecting each input shift register read output terminal to a corresponding output shift register write input terminal, m converter circuit output means respectively connected to the corresponding output terminals of said output shift register means, a loop-connected parallel-read n-stage control shift register means, means for synchronously performing every shift in every shift register at the same primary digital highway bit rate, write control input means on each of said input and control shift register means for causing that shift register to write instead of to shift, means for connecting the write control inputs of said input shift register means to read outputs of said control shift register means in accordance with the rank of said input shift register means, and means for applying an initial signal to the write control input of said control shift register means for initiating an operation said control shift register.
Claim 2
Dependent Claim
309 words
A converter circuit for a PCM switching system, means for connecting up to a predetermined number of primary digital multiplex highways with synchronized time frames and bit rates to said converter circuit, said converter comprising means for converting primary multiplex highway channel data from a serial mode into a parallel mode, means for multiplexing said parallel mode channel data to form a supermultiplex highway of signals, means for providing a plurality of cyclically recurring time slots with as many parallel mode channels as there are primary digital multiplex highway connections on said converter circuit, said channel data being arranged in n-bit words, m-1 serial-write, serial-read output shift register means in said converter circuit, each of said m-1 shift register means having one stage less than the number of stages in the preceding shift register means, m parallel-write serial-read input shift register means for receiving signals from individually associated ones of said primary highways, each of said input shift register means having n-stages, means for connecting each input shift register read output terminal to a corresponding output shift register write input terminal, m converter circuit output means respectively connected to the corresponding output terminals of said output shift register means, a loop-connected parallel-read n-stage control shift register means, means for synchronously performing every shift in every shift register at the same primary digital highway bit rate, write control input means on each of said input and control shift register means for causing that shift register to write instead of to shift, means for connecting the write control inputs of said input shift register means to read outputs of said control shift register means in accordance with the rank of said input shift register means, and means for applying an initial signal to the write control input of said control shift register means for initiating an operation said control shift register.
Claim 3
Dependent Claim
48 words
The converter circuit of claim 1 wherein n=8 so that there are 8 bits in every channel of a primary multiplex highway and wherein m=8 so that there are 8 inputs and 8 input shift register means, 7 output register means, and an 8-stage control shift register means.
Claim 4
Dependent Claim
71 words
A converter circuit, according to claim 1, for converting parallel mode channel data from supermultiplex highway signals into serial mode channel data, and means for demultiplexing said parallel mode channel data for delivering outgoing primary digital multiplex highway signals, said converter circuit inputs being connected from transmission wires of said supermultiplex highway, and the output of said converter circuit being connected to lines for transmitting said outgoing primary digital multiplex highway.
Claim 5
Dependent Claim
36 words
Converter circuits according to claim 1, there being a plurality of said converter circuits arranged in a set having multiplexed outputs, the output supermultiplex bit rate being a multiple of a converter circuit output multiplex rate.
Claim 6
Dependent Claim
54 words
Converter circuits according to claim 1, there being a plurality of said converter circuits arranged in a converter circuit set having its inputs connected from said primary digital multiplex highways responsive to demultiplexing multiplex highway signals having a bit rate that is a multiple of the bit rate of a primary digital multiplex highway.
References Cited (Backward Citations)
FR2225898A1
Cited
US3821480A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-06-04 | 1982-12-04 | 1983-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-06-04 | 1986-12-04 | 1987-06-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-06-04 | 1990-12-04 | 1991-06-05 | $7700.00 | Window Closed / Lapsed |