Method for increasing the radiation resistance of charge storage semiconductor devices

Claim 1

The method of manufacturing integrated circuit devices having a reduced susceptibility to radiation induced loss of charged data states in which a semiconductor substrate having a substantially uniform predetermined impurity concentration of a first conductivity type and having a predetermined thickness is sequentially exposed to a plurality of semiconductor processing steps which include at least two high temperature processing steps requiring processing temperatures in excess of about 500° C., one of which is used to form surface device p-n junction regions having a predetermined maximum depletion depth in a normal operating environment, characterized by the step of providing in a portion of the substrate a buried layer of increased first impurity concentration before the last of the high temperature processing steps so as to provide at the completion of all of the processing steps a buried non-degenerate impurity concentration profile having a maximum concentration of between 5×10 16 and 1×10 19 impurity atoms per cubic centimeter and being one to four orders of magnitude greater than the predetermined impurity concentration of the substrate and the buried layer being at a depth throughout its extent so as to be deeper than the regions of substantial electrical activity of devices formed on the surface of the substrate, whereby portions of the substrate above and below said buried layer remain at said predetermined impurity concentration.

Claim 2

The method of manufacturing integrated circuit devices having a reduced susceptibility to radiation induced loss of charged data states in which a semiconductor substrate having a substantially uniform predetermined impurity concentration of a first conductivity type and having a predetermined thickness is sequentially exposed to a plurality of semiconductor processing steps which include at least two high temperature processing steps requiring processing temperatures in excess of about 500° C., one of which is used to form surface device p-n junction regions having a predetermined maximum depletion depth in a normal operating environment, characterized by the step of providing in a portion of the substrate a buried layer of increased first impurity concentration before the last of the high temperature processing steps so as to provide at the completion of all of the processing steps a buried non-degenerate impurity concentration profile having a maximum concentration of between 5×10 16 and 1×10 19 impurity atoms per cubic centimeter and being one to four orders of magnitude greater than the predetermined impurity concentration of the substrate and the buried layer being at a depth throughout its extent so as to be deeper than the regions of substantial electrical activity of devices formed on the surface of the substrate, whereby portions of the substrate above and below said buried layer remain at said predetermined impurity concentration.