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US4504744A Expired / Lapsed US ⏱️ 0.0 years remaining

Schottky TTL integrated logic gate circuit with reduced speed power product

Assignee: National Semiconductor Corp
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Filing: 1983-01-13
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Granted: 1985-03-12
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Expires: 2003-01-13
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Abstract

Abstract An inverter gate using advanced low power Schottky configuration is shown in which a feedback transistor is used to provide input pull up action. The transistor is a minimum area device that occupies less chip area than the elements that it replaces. It also conserves power so that the speed power product is reduced. The circuit further incorporates negative feedback associated with the input bias resistor whereby a smaller resistor can be employed without increasing supply current drain or input current.

Inventors

  • 👤 Ramanatha V. Balakrishnan

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 02:32
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/088; H03K19/01; H03K19/013; H03K19/0136

Claims Analysis

Total Claims: 19
Claim 1
Independent Claim 171 words
A low power inverter gate circuit having input and output terminals wherein said output terminal provides an inverted logic state representation of the input terminal logic state, said circuit comprising; first and second supply rails connectable to a source of operating power; current source transistor means coupled between said first supply rail and said output terminal and having a control terminal; current sink transistor means coupled between said second supply rail and said output terminal and having a control terminal; phase splitter transistor means having a control terminal, a first output coupled to said control terminal of said current source transistor means, and a second output coupled to said control terminal of said current sink transistor means; diode means coupled between said input terminal and said control terminal of said phase splitter transistor means; and active transistor means having a control terminal coupled to said output terminal and controlled terminals coupled between said control terminal of said phase splitter transistor means and said control terminal of said current source transistor means.
Claim 2
Dependent Claim 171 words
A low power inverter gate circuit having input and output terminals wherein said output terminal provides an inverted logic state representation of the input terminal logic state, said circuit comprising; first and second supply rails connectable to a source of operating power; current source transistor means coupled between said first supply rail and said output terminal and having a control terminal; current sink transistor means coupled between said second supply rail and said output terminal and having a control terminal; phase splitter transistor means having a control terminal, a first output coupled to said control terminal of said current source transistor means, and a second output coupled to said control terminal of said current sink transistor means; diode means coupled between said input terminal and said control terminal of said phase splitter transistor means; and active transistor means having a control terminal coupled to said output terminal and controlled terminals coupled between said control terminal of said phase splitter transistor means and said control terminal of said current source transistor means.
Claim 3
Dependent Claim 36 words
The circuit of claim 1 wherein said diode means comprise a plurality of diodes, each one coupling a separate one of a plurality of input terminals to the control terminal of said phase splitter transistor means.
Claim 4
Dependent Claim 14 words
The circuit of claim 1 wherein said transistor means comprise metal oxide semiconductor transistors.
Claim 5
Dependent Claim 56 words
The circuit of claim 1 wherein said control terminal of said current source transistor means is coupled by way of first and second series connected resistors to said first supply rail and a third resistor is coupled between the juncture of said first and second resistors and said control terminal of said phase splitter transistor means.
Claim 6
Dependent Claim 12 words
The circuit of claim 1 wherein said transistor means comprise bipolar transistors.
Claim 7
Dependent Claim 23 words
The circuit of claim 5 wherein said current sink transistor means and said phase splitter transistor means comprise Schottky diode clamped bipolar transistors.
Claim 8
Dependent Claim 24 words
The circuit of claim 6 wherein said current source bipolar transistor means include a Schottky diode coupled in series therewith to said output terminal.
Claim 9
Dependent Claim 86 words
In a logic circuit employing transistor devices that have controlled terminals and a control terminal said circuit comprising a transmission inverter gate having a totem pole output stage that includes a pull up device and a pull down device driven by a phase splitter device the improvement comprising: a feedback transistor device having its control terminal coupled to the output of said gate and its controlled terminals coupled between the control terminal of said phase splitter device and the control terminal of said pull up device.
Claim 10
Dependent Claim 86 words
In a logic circuit employing transistor devices that have controlled terminals and a control terminal said circuit comprising a transmission inverter gate having a totem pole output stage that includes a pull up device and a pull down device driven by a phase splitter device the improvement comprising: a feedback transistor device having its control terminal coupled to the output of said gate and its controlled terminals coupled between the control terminal of said phase splitter device and the control terminal of said pull up device.
Claim 11
Dependent Claim 15 words
The improvement of claim 8 wherein said transistor devices are of metal oxide semiconductor construction.
Claim 12
Dependent Claim 13 words
The improvement of claim 8 wherein said transistors are of bipolar device construction.
Claim 13
Dependent Claim 19 words
The improvement of claim 10 wherein said pull down and said phase splitter devices are of bipolar Schottky construction.
Claim 14
Dependent Claim 144 words
A logic inverter gate circuit having input and output terminals, said circuit comprising: first and second supply terminals connectable to a source of operating power; a first transistor having a collector coupled to said first supply terminal, an emitter coupled to said output terminal and a base; a second transistor having an emitter coupled to said second supply terminal a collector coupled to said output terminal, and a base; a third transistor having an emitter coupled to said base of said second transistor, a collector coupled to said base of said first transistor, and a base a first diode coupled between said input terminal and said base of said third transistor; and a fourth transistor having an emitter coupled to said base of said third transistor, a base coupled to said output terminal and a collector coupled to said collector of said third transistor.
Claim 15
Dependent Claim 144 words
A logic inverter gate circuit having input and output terminals, said circuit comprising: first and second supply terminals connectable to a source of operating power; a first transistor having a collector coupled to said first supply terminal, an emitter coupled to said output terminal and a base; a second transistor having an emitter coupled to said second supply terminal a collector coupled to said output terminal, and a base; a third transistor having an emitter coupled to said base of said second transistor, a collector coupled to said base of said first transistor, and a base a first diode coupled between said input terminal and said base of said third transistor; and a fourth transistor having an emitter coupled to said base of said third transistor, a base coupled to said output terminal and a collector coupled to said collector of said third transistor.
Claim 16
Dependent Claim 40 words
The circuit of claim 12 further comprising current conducting means coupled between said base of said second transistor and said second supply terminal and, first resistor means coupled between said collector of said third transistor and said first supply terminal.
Claim 17
Dependent Claim 25 words
The circuit of claim 13 further including second diode means coupled in series with said emitter of said first transistor and poled to conduct therewith.
Claim 18
Dependent Claim 56 words
The circuit of claim 14 wherein said first resistor means includes a tap that is connected to one end of a second resistor means the other end of which is connected to said base of said third transistor whereby the value of said second resistor can be reduced to a low value without introducing excessive loading.
Claim 19
Dependent Claim 19 words
The circuit of claim 14 wherein said second diode, and said second and third transistors are of Schottky construction.

References Cited (Backward Citations)

US3510685A Cited
US3751680A Cited
US4321490A Cited
JPS55163918A Cited
JPS5634229A Cited
US4415817A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1988-03-11 1988-09-10 1989-03-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1992-03-11 1992-09-10 1993-03-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1996-03-11 1996-09-10 1997-03-12 $7700.00 Window Closed / Lapsed

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