Computer graphics generator

Claim 2

Graphics circuitry for use in a computer system including at least one video display unit, and a central processor having means for generating peripheral address signals to select said display unit, and means for generating data signals to be displayed on said unit, said graphics circuitry comprising: memory means responsive to memory address signals for receiving and storing data, means responsive to selective ones of said peripheral address signals for applying a first plurality of said data signals to said graphics memory as memory address signals, and means responsive to selective ones of said peripheral address signals for entering a second plurality of said data signals into said memory at memory locations specified by said first plurality of data signals as graphics data.

Claim 3

Graphics circuitry according to claim 1 wherein said processor includes means responsive to a control signal for temporarily suspending operation and said graphics circuitry further comprises means responsive to selected ones of said peripheral address signals for generating said control signal.

Claim 4

Graphics circuitry according to claim 1 wherein said processor includes means for generating a write signal and wherein said entering means comprises means responsive to said write signal for receiving and storing said data signals, and means for controlling said memory means to enter said stored data signals into said memory means, said controlling means starting operation in response to selective ones of said peripheral address signals and thereafter operating independently from said processor.

Claim 5

Graphics circuitry according to claim 1 wherein said applying means comprises, means responsive to selective ones of said peripheral address signals for receiving and storing said data signals, means responsive to selective ones of said peripheral address signals for incrementing and decrementing said stored data signals, and means responsive to stored data signals for applying said stored signals as memory address signals to said memory means.

Claim 6

Graphics circuitry according to claim 4 wherein said storing means comprises a bi-directional counter.

Claim 7

Graphics circuitry for use in a computer system including at least one video screen display unit, and a central processor having means to generate data signals and control signals, said graphics circuitry comprising, memory means having a plurality of memory locations, said memory means being responsive to row and column memory address signals for accessing one of said memory locations which contains information to be displayed on said screen at a physical location specified by said row and column addresses, and means responsive to a plurality of said data signals for repetitively converting selected ones of said data signals into row and column address signals for application to said memory means as a plurality of row and column address signals.

Claim 8

Graphics circuitry for use in a computer system including at least one video screen display unit, and a central processor having means to generate data signals and control signals, said graphics circuitry comprising, memory means having a plurality of memory locations, said memory means being responsive to row and column memory address signals for accessing one of said memory locations which contains information to be displayed on said screen at a physical location specified by said row and column addresses, and means responsive to a plurality of said data signals for repetitively converting selected ones of said data signals into row and column address signals for application to said memory means as a plurality of row and column address signals.

Claim 9

Graphics circuitry according to claim 6 wherein said video screen display unit includes character generation circuitry for displaying alpha and numeric characters, said character generation circuitry generating line and column position signals specifying the position of the screen at which information is to be displayed and synchronization signals, and said graphics circuitry further comprises means responsive to said line and column position signals for generating row and column memory address signals, and means responsive to selected ones of said control signals for applying row and column memory address signals produced by said generating means to said memory means to cause a sequential display of information in each of said memory locations and responsive to selected ones of said control signals for applying said memory row and column address signals produced by said converting means to said memory means for causing display of information at a single location on said screen.

Claim 10

Graphics circuitry according to claim 7 wherein said applying means comprises a multiplexer having inputs for receiving memory address signals produced by said generating means and inputs for receiving memory address inputs generated by said converting means and an output connected to address port of said memory means, and said applying means further comprises means responsive to selected ones of said control signals for connecting selected multiplexer inputs to said multiplexer output.

Claim 11

Graphics circuitry for use in a computer system including at least one video screen display unit, and a central processor having means for generating peripheral address signals to select said display unit, and means for generating data signals to be displayed on said unit, said graphics circuitry comprising, memory means having a plurality of memory locations, said memory means being responsive to row and column memory address signals for accessing one of said memory locations which contains information to be displayed on said screen at a physical location specified by said row and column addresses, and means responsive to selective ones of said peripheral address signals for converting selective ones of said data signals into row and column address signals for application to said memory means, and means responsive to selective ones of said peripheral address signals for entering selective ones of said data signals into said memory as graphics data.

Claim 12

Graphics circuitry for use in a computer system including at least one video screen display unit, and a central processor having means for generating peripheral address signals to select said display unit, and means for generating data signals to be displayed on said unit, said graphics circuitry comprising, memory means having a plurality of memory locations, said memory means being responsive to row and column memory address signals for accessing one of said memory locations which contains information to be displayed on said screen at a physical location specified by said row and column addresses, and means responsive to selective ones of said peripheral address signals for converting selective ones of said data signals into row and column address signals for application to said memory means, and means responsive to selective ones of said peripheral address signals for entering selective ones of said data signals into said memory as graphics data.

Claim 13

Graphics circuitry according to claim 9 wherein said video screen display unit includes character generation circuitry for displaying alpha and numeric characters, said character generation circuitry generating line and column position signals specifying the position of the screen at which information is to be displayed and synchronization signals, and said graphics circuitry further comprises, means responsive to said line and column position signals for generating row and column memory address signals, and means responsive to selected ones of said peripheral address signals for applying row and column memory address signals produced by said generating means to said memory means to cause a sequential display of information in each of said memory locations and responsive to selected ones of said peripheral address signals for applying said memory row and column address signals generated by said converting means to said memory means for causing display of information at a single location on said screen.

Claim 14

Graphics circuitry according to claim 10 wherein said applying means comprises, means responsive to selective ones of said peripheral address signals for receiving and storing said data signals, means responsive to selective ones of said peripheral address signals for incrementing and decrementing said stored data signals, and means responsive to stored data signals for applying said stored signals as memory address signals to said memory means.

Claim 15

Graphics circuitry according to claim 11 wherein said applying means further comprises a multiplexer having inputs for receiving memory address signals produced by said generating means and inputs for receiving memory address inputs stored in said storing means and an output connected to address port of said memory means, and said applying means further comprises means responsive to selected ones of said peripheral address signals for connecting selected multiplexer inputs to said multiplexer output.

Claim 16

Graphics circuitry according to claim 12 wherein said processor includes means for generating a write signal and wherein said entering means comprises means responsive to said write signal for receiving and storing said data signals, and means for controlling said memory means to enter said stored data signals into said memory means, said controlling means starting operation in response to selective ones of said peripheral address signals and thereafter operating independently from said processor under control of said synchronization signals generated by said character generation circuitry.

Claim 17

Graphics circuitry according to claim 13 wherein said storing means comprises a bi-directional counter for storing row address signals and a bi-directional counter for storing column address signals.

Claim 18

Graphics circuitry for use in a computer system including at least one video screen display unit, said unit including character generation circuitry for displaying alpha and numeric characters, said character generation circuitry generating line and column position signals specifying the position of the screen at which information is to be displayed and synchronization signals, and a central processor having means for generating peripheral address signals to select said display unit, and means for generating data signals to be displayed on said unit, said graphics circuitry comprising, a random access memory having a plurality of memory locations, said memory being responsive to row and column memory address signals for accessing one of said memory locations which contains information to be displayed on said screen at a physical location specified by said row and column addresses, a command decoder responsive to selected ones of said peripheral address signals for generating a plurality of memory control signals, two bi-directional counters responsive to selective ones of said memory control signals for receiving and storing selected ones of said data signals, means responsive to selective ones of said memory control signals for selectively incrementing and decrementing said counters, read-only memory means responsive to said line and column position signals for generating row and column memory address signals, a multiplexer having inputs for receiving memory address signals produced by said read-only memory means and inputs for receiving data signals stored in said counters and an output connected to address port of said random access memory, and means responsive to selected ones of said memory control signals for connecting selected multiplexer inputs to said multiplexer output.

Claim 19

Graphics circuitry for use in a computer system including at least one video screen display unit, said unit including character generation circuitry for displaying alpha and numeric characters, said character generation circuitry generating line and column position signals specifying the position of the screen at which information is to be displayed and synchronization signals, and a central processor having means for generating peripheral address signals to select said display unit, and means for generating data signals to be displayed on said unit, said graphics circuitry comprising, a random access memory having a plurality of memory locations, said memory being responsive to row and column memory address signals for accessing one of said memory locations which contains information to be displayed on said screen at a physical location specified by said row and column addresses, a command decoder responsive to selected ones of said peripheral address signals for generating a plurality of memory control signals, two bi-directional counters responsive to selective ones of said memory control signals for receiving and storing selected ones of said data signals, means responsive to selective ones of said memory control signals for selectively incrementing and decrementing said counters, read-only memory means responsive to said line and column position signals for generating row and column memory address signals, a multiplexer having inputs for receiving memory address signals produced by said read-only memory means and inputs for receiving data signals stored in said counters and an output connected to address port of said random access memory, and means responsive to selected ones of said memory control signals for connecting selected multiplexer inputs to said multiplexer output.

Claim 20

Graphics circuitry according to claim 15 wherein said processor includes means for generating a write signal and means responsive to a control signal for temporarily suspending operation and wherein said command decoder comprises, means responsive to selected ones of said peripheral address signals and to said write signal for generating said control signal, and means for controlling said random access memory to enter data signals into said random access memory, said controlling means starting operation in response to selective ones of said peripheral address signals and thereafter operating independently from said processor under control of said synchronization signals generated by said character generation circuitry.

Claim 21

Graphics circuitry according to claim 16 wherein said random access memory is a dynamic random access memory.

Claim 22

Graphics circuitry for use in a computer system including at least one video screen display unit having means to generate video address signals on a video address bus, and a central processor having means to generate data signals on a data bus, address signals on an address bus and control signals on a control bus, said graphics circuitry comprising, a graphics memory having a plurality of memory locations, and an address port, said memory being responsive to address signals at said address port for accessing one of said memory locations, and multiplexer means for selectively applying signals on said data bus and said video address bus to said memory address port as address signals.

Claim 23

Graphics circuitry for use in a computer system including at least one video screen display unit having means to generate video address signals on a video address bus, and a central processor having means to generate data signals on a data bus, address signals on an address bus and control signals on a control bus, said graphics circuitry comprising, a graphics memory having a plurality of memory locations, and an address port, said memory being responsive to address signals at said address port for accessing one of said memory locations, and multiplexer means for selectively applying signals on said data bus and said video address bus to said memory address port as address signals.

Claim 24

Graphics circuitry according to claim 18 wherein said multiplexer means is responsive to signals on said address bus for applying signals on said video address bus and said data bus to said memory address port.

Claim 25

Graphics circuitry according to claim 18 wherein said processor includes means responsive to a control signal for temporarily suspending operation and said graphics circuitry further comprises means responsive to selected ones of said address signals on said address bus for generating said control signal.

Claim 26

Graphics circuitry according to claim 18 wherein said processor includes means for generating a write signal and wherein said graphics circuitry further comprises means responsive to said write signal for receiving and storing data signals on said data bus, and means for controlling said graphics memory to enter said stored data signals into said graphics memory, said controlling means starting operation in response to selective ones of said address signals on said address bus and thereafter operating independently from said processor.

Claim 27

Graphics circuitry according to claim 18 further comprising, means responsive to selective ones of said address signals on said address bus for receiving and storing data signals on said data bus, means responsive to selective ones of said address signals on said address bus for incrementing and decrementing said stored data signals, and means responsive to stored data signals for applying said stored signals as memory address signals to said memory means.

Claim 28

Graphics circuitry according to claim 22 wherein said receiving and storing means comprises a bi-directional counter.