Patent US4500986A successfully refreshed from Google Patents.
US4500986A
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Asymmetrical time division matrix apparatus
Assignee: Rockwell Firstpoint Contact Corp
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Filing: 1983-01-31
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Granted: 1985-02-19
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Expires: 2003-01-31
Abstract
Abstract Asymmetrical time division multiplex switch for use in a nonblocking switch matrix. This design reduces parts required to configure the switch matrix since the prior art typically uses symmetrical switches wherein one of the inputs and outputs of a plurality of switches are connected in parallel to perform the total switch matrix function. The asymmetrical design reduces parts count and accordingly increases reliability of the total device.
Inventors
- 👤 John H. Carver
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 07:49
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/08
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
453 words
Time division multiplex apparatus having time and space switching capability comprising, in combination: first means for supplying N signal groups each signal group having M sets of time division multiplexed signals where N and M are both integers greater than 1; signal memory second means including input means, output means and addressing control means having first and second (N * M) signal storage location sets where "*" is a multiplication symbol; sequential addressing third means for providing sequentially occurring and repeating first address signals; input buffer serial to parallel fourth means, connected to said first, second and third means, for supplying signals as received from said first means to said first and second signal storage locations of said second means at times determined by addressing signals received from said third means; fifth means for supplying second address signals; address memory sixth means, including address signal input means, control means and output means, for storing (N * M) signal addresses wherein each signal address is (K+1) bits in length, where K is equal to log 2 (N * M), at storage locations determined by signals applied at said control means thereof; address memory multiplex seventh means, including clock input means, first and second address signal input and signal output means, and connected to said third, fifth and sixth means for supplying read and write addresses to said sixth means in accordance with clock signals supplied to said clock input means; signal memory multiplex eighth means, including clock means, first and second address signal input means and signal output means, connected to said second, third and sixth means, for passing K addressing bits from said third and sixth means to each of said first and second signal storage location sets of said means; ninth means connecting said sixth means to said second means for supplying the remaining addressing bit of said (K+1) bits in said sixth means to said first and second signal storage location sets in said second means; parallel to serial output tenth means, including signal input, control input and N output means, connected to said second and third means for converting parallel signals from said first storage location set of said second means to serial output signals at one of said N output means in accordance with address signals received at said control means thereof from said third means; and parallel to serial output eleventh means, including signal input, control input and N output means, connected to said second and third means for converting parallel signals from said second storage location set of said second means to serial output signals at one of said N output means in accordance with address signals received at said control means thereof from said third means.
Claim 2
Dependent Claim
453 words
Time division multiplex apparatus having time and space switching capability comprising, in combination: first means for supplying N signal groups each signal group having M sets of time division multiplexed signals where N and M are both integers greater than 1; signal memory second means including input means, output means and addressing control means having first and second (N * M) signal storage location sets where "*" is a multiplication symbol; sequential addressing third means for providing sequentially occurring and repeating first address signals; input buffer serial to parallel fourth means, connected to said first, second and third means, for supplying signals as received from said first means to said first and second signal storage locations of said second means at times determined by addressing signals received from said third means; fifth means for supplying second address signals; address memory sixth means, including address signal input means, control means and output means, for storing (N * M) signal addresses wherein each signal address is (K+1) bits in length, where K is equal to log 2 (N * M), at storage locations determined by signals applied at said control means thereof; address memory multiplex seventh means, including clock input means, first and second address signal input and signal output means, and connected to said third, fifth and sixth means for supplying read and write addresses to said sixth means in accordance with clock signals supplied to said clock input means; signal memory multiplex eighth means, including clock means, first and second address signal input means and signal output means, connected to said second, third and sixth means, for passing K addressing bits from said third and sixth means to each of said first and second signal storage location sets of said means; ninth means connecting said sixth means to said second means for supplying the remaining addressing bit of said (K+1) bits in said sixth means to said first and second signal storage location sets in said second means; parallel to serial output tenth means, including signal input, control input and N output means, connected to said second and third means for converting parallel signals from said first storage location set of said second means to serial output signals at one of said N output means in accordance with address signals received at said control means thereof from said third means; and parallel to serial output eleventh means, including signal input, control input and N output means, connected to said second and third means for converting parallel signals from said second storage location set of said second means to serial output signals at one of said N output means in accordance with address signals received at said control means thereof from said third means.
Claim 3
Dependent Claim
399 words
Time division multiplex apparatus having time and space switching capability comprising, in combination: first means for supplying two sets of N signal groups each signal group having M sets of time division multiplexed signals where N and M are both integers greater than 1; signal memory second means including input means, output means and addressing control means having first and second (N * M) signal storage location sets where "*" is a multiplication symbol; sequential addressing third means for providing sequentially occurring and repeating first address signals; input buffer serial to parallel fourth means, connected to said first, second and third means, for supplying signals as received from said first means to said first and second signal storage locations of said second means at times determined by addressing signals received from said third means; fifth means for supplying second address signals; address memory sixth means, including address signal input means, control means and output means, for storing (N * M) signal addresses wherein each signal address is (K+1) bits in length, where K is equal to log 2 (N * M), at storage locations determined by signals applied at said control means thereof; address memory multiplex seventh means, including clock input means, first and second address signal input and signal output means, and connected to said third, fifth and sixth means for supplying read and write addresses to said sixth means in accordance with clock signals supplied to said clock input means; signal memory multiplex eighth means, including clock means, first and second address signal input means and signal output means, connected to said second, third and sixth means, for passing K addressing bits from said third and sixth means to each of said first and second signal storage location sets of said second means; ninth means connecting said sixth means to said second means for supplying the remaining addressing bit of said (K+1) bits in said sixth means to said first and second signal storage location sets in said second means; and parallel to serial output tenth means, including signal input, control input and N output means, connected to said second and third means for converting parallel signals from each of said first and second storage location sets of said second means to serial output signals at one of said N output means in accordance with address signals received at said control means thereof from said third means.
Claim 4
Dependent Claim
399 words
Time division multiplex apparatus having time and space switching capability comprising, in combination: first means for supplying two sets of N signal groups each signal group having M sets of time division multiplexed signals where N and M are both integers greater than 1; signal memory second means including input means, output means and addressing control means having first and second (N * M) signal storage location sets where "*" is a multiplication symbol; sequential addressing third means for providing sequentially occurring and repeating first address signals; input buffer serial to parallel fourth means, connected to said first, second and third means, for supplying signals as received from said first means to said first and second signal storage locations of said second means at times determined by addressing signals received from said third means; fifth means for supplying second address signals; address memory sixth means, including address signal input means, control means and output means, for storing (N * M) signal addresses wherein each signal address is (K+1) bits in length, where K is equal to log 2 (N * M), at storage locations determined by signals applied at said control means thereof; address memory multiplex seventh means, including clock input means, first and second address signal input and signal output means, and connected to said third, fifth and sixth means for supplying read and write addresses to said sixth means in accordance with clock signals supplied to said clock input means; signal memory multiplex eighth means, including clock means, first and second address signal input means and signal output means, connected to said second, third and sixth means, for passing K addressing bits from said third and sixth means to each of said first and second signal storage location sets of said second means; ninth means connecting said sixth means to said second means for supplying the remaining addressing bit of said (K+1) bits in said sixth means to said first and second signal storage location sets in said second means; and parallel to serial output tenth means, including signal input, control input and N output means, connected to said second and third means for converting parallel signals from each of said first and second storage location sets of said second means to serial output signals at one of said N output means in accordance with address signals received at said control means thereof from said third means.
Claim 5
Dependent Claim
345 words
Time division multiplex apparatus having time and space switching capability comprising, in combination: first means for supplying two sets of signal groups each signal group having time division multiplexed signals; signal memory second means including input means, output means and addressing control means having first and second signal storage location sets; sequential addressing third means for providing sequentially occurring first address signals; input buffer fourth means, connected to said first, second and third means, for supplying signals as received from said first means to said first and second signal storage locations of said second means at times determined by addressing signals received from said third means; fifth means for supplying second address signals; address memory sixth means, including address signal input means, control means and output means, for storing signal addresses at storage locations determined by signals applied at said control means thereof; address memory multiplex seventh means, including clock input means, first and second address signal input and signal output means, and connected to said third, fifth and sixth means for supplying read and write addresses to said sixth means in accordance with clock signals supplied to said clock input means; signal memory multiplex eighth means, including clock means, first and second address signal input means and signal output means, connected to said second, third and sixth means, for passing addresses from said third and sixth means to each of said first and second signal storage location sets of said second means; ninth means connecting said sixth means to said second means for supplying a remaining addressing bit of the bits received from said sixth means to said first and second signal storage location sets in said second means; and parallel to serial output tenth means, including signal input, control input and output means, connected to said second and third means for converting parallel signals from each of said first and second storage location sets of said second means to serial output signals at one of said output means in accordance with address signals received at said control means thereof from said third means.
Claim 6
Dependent Claim
345 words
Time division multiplex apparatus having time and space switching capability comprising, in combination: first means for supplying two sets of signal groups each signal group having time division multiplexed signals; signal memory second means including input means, output means and addressing control means having first and second signal storage location sets; sequential addressing third means for providing sequentially occurring first address signals; input buffer fourth means, connected to said first, second and third means, for supplying signals as received from said first means to said first and second signal storage locations of said second means at times determined by addressing signals received from said third means; fifth means for supplying second address signals; address memory sixth means, including address signal input means, control means and output means, for storing signal addresses at storage locations determined by signals applied at said control means thereof; address memory multiplex seventh means, including clock input means, first and second address signal input and signal output means, and connected to said third, fifth and sixth means for supplying read and write addresses to said sixth means in accordance with clock signals supplied to said clock input means; signal memory multiplex eighth means, including clock means, first and second address signal input means and signal output means, connected to said second, third and sixth means, for passing addresses from said third and sixth means to each of said first and second signal storage location sets of said second means; ninth means connecting said sixth means to said second means for supplying a remaining addressing bit of the bits received from said sixth means to said first and second signal storage location sets in said second means; and parallel to serial output tenth means, including signal input, control input and output means, connected to said second and third means for converting parallel signals from each of said first and second storage location sets of said second means to serial output signals at one of said output means in accordance with address signals received at said control means thereof from said third means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-02-19 | 1988-08-20 | 1989-02-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-02-19 | 1992-08-20 | 1993-02-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-02-19 | 1996-08-20 | 1997-02-19 | $7700.00 | Window Closed / Lapsed |