Symmetrical time division matrix and a network equipped with this kind of matrix

Claim 2

A symmetrical time-division matrix for switching input time-slots of a first set of input series PCM junctions towards output time-slots of a second set of output series PCM junctions, said matrix comprising: parallelizing means for receiving simultaneously in serial form said input time-slots from said input series PCM junctions and delivering successively in parallel form said input time-slots; time-division switching means for receiving said input time-slots from said parallelizing means according to a first order, switching said input time-slots into said output time-slots according to a second order, and delivering successively in parallel form said output time-slots according to said second order; and serializing means for receiving from said timedivision switching means said output time-slots, for selecting an output series PCM junction for a time-slot based solely on the position of said time-slot in the succession of output time-slots, and for delivering simultaneously in serial form said output time-slots to said output series PCM junctions.

Claim 3

A matrix as claimed in claim 1, further comprising a counter for providing to said parallelizing means signals for controlling said delivering of the input time slots, and providing to said time division switching means signals for controlling said memorizing according to a first order.

Claim 4

A matrix as claimed in claim 2, thurther comprising a counter for providing to said time divison switching means signals for controlling said delivering according to a second order, and providing to said serializing means signals for controlling said delivering of the output time slots.

Claim 5

A matrix as claimed in claim 3, further comprising means for modifying said second order under the control of an external signal between the delivering of two successive of said output time-slots.

Claim 6

A matrix as claimed in claim 1, wherein said first set comprises eight input junctions, said second set comprises eight output junctions; said input and output junctions comprising 32 time-slots coded over 8 bits.

Claim 7

A time-division network for switching at least one input time-slot of one of m × n input PCM series junctions to one output time-slot of one of m × n output PCM series junctions, said network comprising: an input stage comprising a symmetrical time-division matrices, each of said matrices having one free input, n other inputs connected to n of said input connections, and n+1 outputs; an intermediate stage divided into n + 1 separate pluralities of symmetrical time-division matrices, each of said pluralities substantially forming a plan, and each of said plans being connected to one output of each of said matrices of the input stage; the symmetrical time-division matrices of each of said plans being interconnected for relating at least one input of said plan to one output of said plan; an output stage comprising m symmetrical time-division matrices, each of said matrices having n+1 inputs, one free output, and n other outputs connected to n of said output junctions; and each of said plans being connected to one input of each of said matrices of the output stage; and control means for fixing at least one route between one of said input junctions and one of said output junctions.

Claim 8

A time-division network for switching at least one input time-slot of one of m × n input PCM series junctions to one output time-slot of one of m × n output PCM series junctions, said network comprising: an input stage comprising a symmetrical time-division matrices, each of said matrices having one free input, n other inputs connected to n of said input connections, and n+1 outputs; an intermediate stage divided into n + 1 separate pluralities of symmetrical time-division matrices, each of said pluralities substantially forming a plan, and each of said plans being connected to one output of each of said matrices of the input stage; the symmetrical time-division matrices of each of said plans being interconnected for relating at least one input of said plan to one output of said plan; an output stage comprising m symmetrical time-division matrices, each of said matrices having n+1 inputs, one free output, and n other outputs connected to n of said output junctions; and each of said plans being connected to one input of each of said matrices of the output stage; and control means for fixing at least one route between one of said input junctions and one of said output junctions.

Claim 9

A network as claimed in claim 6, wherein said control means comprise: a central unit for fixing a first part of said route between said one input junction and one of said plans, and a third part of said route between said one plan and said one output junction; and n+1 separate control circuits connected to respectively each of said plans; the separate control circuit connected to said one plan fixing under the control of said central unit, a second part of said route between said first and third part.

Claim 10

A network as claimed in claim 7, wherein said PCM junctions comprises 32 channels coded from 8 bits, and said symmetrical time-division matrices have n+1 = 8 inputs and n+1 = 8 outputs.

Claim 11

A network as claimed in claim 8, wherein each of said plans is divided into three successive interconnected switching sub-stages.

Claim 12

A network as claimed in claim 9, wherein the number m is equal to 64, and each of said successive sub-stages comprises 8 symmetrical time-divided matrices.

Claim 13

A network as claimed in claim 8, wherein each of said plans is divided into two parallel sub-plans, each of said sub-plans being divided into a first, a medium, and a third interconnected switching sub-stages; and the medium sub-stages of two sub-plans of one plan being interconnected.

Claim 14

A networkk as claimed in claim 11, wherein the number m is equal to 128; the first and the third sub-stages of each sub-plan comprising respectively eight symmetrical time-division matrices, and the medium sub-stage of each sub-plan comprising 16 symmetrical time-division matrices.

Claim 15

A network as claimed in claim 8, wherein each of said plans comprises a sub-network composed of symmetrical time-division matrices interconnected for forming a square matrice without blocking.

Claim 16

A network as claimed in claim 13, wherein the number m is 32, and each sub-network comprises 16 symmetrical time-division matrices.

Claim 17

A network as claimed in claim 13, wherein the number m is equal to 16, and each sub network comprises 4 symmetrical time-division matrices.