Method and apparatus for standardizing nonstandard video signals

Claim 3

The method of claim 1 wherein steps (a) and (c) include cyclically and sequentially writing into and reading from the three line memories, respectively, the writing and reading steps occurring in different memories.

Claim 4

The method of claim 1 wherein the step of writing is accomplished at a clock rate different than the clock rate for the reading step.

Claim 5

The method of claim 1 wherein step (d) includes low pass filtering of the data to obtain luminance information.

Claim 6

The method of claim 1 wherein the shifting of the sampling window is accomplished by: (a) transmitting the read out signals to a serial to parallel shift register having a plurality of outputs; (b) switching between selected ones of said outputs every horizontal line so that every line has a different sampling window than the immediately preceding line and the same sampling window as the second immediately preceding line, whereby the required N.T.S.C. phase relationship of chrominance to color subcarrier and luminance to the horizontal scan frequency are provided.

Claim 7

Apparatus for correcting color video signals represented in digital form having a horizontal scan frequency which is an even harmonic of the color subcarrier to an N.T.S.C. interlaced color video signal having N.T.S.C. luminance and chrominance components and being compatible with and superimposable on other N.T.S.C. color video signals comprising: (a) at least one memory for storing a horizontal line of digitized video signals; (b) means for writing the digitized video signals into said line memory at selected memory locations; (c) means for resetting the source of the video signals to be corrected once during each N.T.S.C. vertical field to synchronize said source to the N.T.S.C. vertical frame; (d) means for reading out the digitized video signals from selected memory locations in said line memory at a clock rate synchronized with an N.T.S.C. source; (e) means for extracting luminance and chrominance information from the read out signals including means for shifting the signal sampling window every other horizontal line for either the chrominance or luminance information to establish the proper N.T.S.C. phase relationship of the chrominance information to the color subcarrier and luminance to horizontal scan frequency; (f) means for combining the information extracted by element (e) to produce the corrected color video signals.

Claim 8

Apparatus for correcting color video signals represented in digital form having a horizontal scan frequency which is an even harmonic of the color subcarrier to an N.T.S.C. interlaced color video signal having N.T.S.C. luminance and chrominance components and being compatible with and superimposable on other N.T.S.C. color video signals comprising: (a) at least one memory for storing a horizontal line of digitized video signals; (b) means for writing the digitized video signals into said line memory at selected memory locations; (c) means for resetting the source of the video signals to be corrected once during each N.T.S.C. vertical field to synchronize said source to the N.T.S.C. vertical frame; (d) means for reading out the digitized video signals from selected memory locations in said line memory at a clock rate synchronized with an N.T.S.C. source; (e) means for extracting luminance and chrominance information from the read out signals including means for shifting the signal sampling window every other horizontal line for either the chrominance or luminance information to establish the proper N.T.S.C. phase relationship of the chrominance information to the color subcarrier and luminance to horizontal scan frequency; (f) means for combining the information extracted by element (e) to produce the corrected color video signals.

Claim 9

The apparatus of claim 6 wherein said apparatus includes three memories each capable of storing digitized video signals corresponding to a horizontal line of video information.

Claim 10

The apparatus of claim 7 wherein the means for writing and reading include: (a) means for clocking the memories during writing and reading by a series of clock pulses; (b) means for gating the clock pulses to the memories; (c) means for controlling the gating means to direct the pulses to selected memories at which reading and writing are to occur.

Claim 11

The apparatus of claim 8 wherein the clocking means includes a clock for writing associated with the signals to be corrected and a clock synchronized with an N.T.S.C. source for reading.

Claim 12

The apparatus of claim 8 wherein the gating means are multiplexers for directing the clock pulses to memories selected by the controlling means.

Claim 13

The apparatus of claim 9 wherein the controlling means include counters which cyclically and sequentially direct the reading and writing clock pulses, respectively, to two of the three memories, but not to the same memory during a given horizontal line of video signals.

Claim 14

The apparatus of claim 6 wherein said apparatus includes a single memory capable of storing digitized video signals corresponding to a horizontal line of video information.

Claim 15

The apparatus of claim 12 wherein the means for writing and reading include: (a) means for clocking the signals into and out of the memories during writing and reading by a series of clock pulses; (b) means for gating the clock pulses to the memory.

Claim 16

The apparatus of claim 6 wherein the luminance extracting means includes a low pass filter.

Claim 17

The apparatus of claim 6 wherein the chrominance extracting means incudes a chroma filter.

Claim 18

The apparatus of claim 6 wherein the sampling window shifting means includes: (a) a serial to parallel shift register having a plurality of outputs receiving the read out signals; (b) means for switching between selected ones of said outputs every horizontal line so that every line has a different sampling window than the immediately preceding line and the same sampling window as the second immediately preceding line whereby the required N.T.S.C. phase relationship of chrominance to color subcarrier is provided.

Claim 19

The apparatus of claim 16 wherein the means for switching includes: (a) a multiplexer outputting said selected ones of said outputs from the serial to parallel register to the combining means; (b) means for controlling the multiplexer so that the outputs selected change every horizontal line.

Claim 20

The apparatus of claim 6 wherein the means for resetting is delay counter clocked by N.T.S.C. horizontal drive and reset by N.T.S.C. vertical drive.