Television synchronizing apparatus

Claim 2

A television signal synchronizer in which incoming video signals are written into memory storage means, said incoming video signals comprising one or more television fields, each of said television fields comprising horizontal line signals having a horizontal blanking interval containing horizontal and burst synchronizing signal components and an active image information portion, said burst signal component being opposite in phase from one of said television fields to another, comprising: coherent memory storage means having preassigned fixed burst phasing for each line store of said memory storage means; signal processing means for developing a composite horizontal sync and burst timing control signal indicative of the timing of said incoming video signal; and delay means responsive to said control signal for delaying the writing into memory of only said active video image information portion(s) so as to write said video image information portion into said memory storage means consistent with said preassigned fixed burst phasing.

Claim 5

A television signal synchronizer in which incoming video signals are written into memory storage means while previously stored video signals are read out of said memory storage means, said incoming video signals comprising one or more television fields, each of said television fields comprising horizontal line signals having a horizontal blanking interval containing horizontal and burst signal synchronizing components and an active image portion, said burst signal components being opposite in phase from one of said television fields to another, comprising: input means coupled to a source of incoming video information signals; input write clock means coupled to said input means for generating a write clock signal synchronized with said incoming video information; first sampling means coupled to said write clock for sampling said video information signal at a rate determined by said write clock signal prior to writing into said memory storage means, said input write clock means developing a ready-to-write signal at the completion of said sampling; said memory storage means having preassigned fixed burst phasing for each line store of said memory storage means; said signal processing means including means for developing a composite horizontal sync and burst timing control signal indicative of the timing of said incoming video signal and delay means responsive to said control signal for delaying said ready-to-write signal; output read clock means for generating a read clock signal; second sampling means coupled to output means and to said read clock for sampling said stored video information signals read out of said storage means, said output clock means developing a ready-to-read signal prior to said sampling; and memory control means coupled to said memory storage means and responsive to said ready-to-write and said ready-to-read signals for developing write and read memory storage control signals whereby only said active video image information portion is read into said memory storage means consistent with said preassigned fixed burst phasing.

Claim 6

A television signal synchronizer in which incoming video signals are written into memory storage means while previously stored video signals are read out of said memory storage means, said incoming video signals comprising one or more television fields, each of said television fields comprising horizontal line signals having a horizontal blanking interval containing horizontal and burst signal synchronizing components and an active image portion, said burst signal components being opposite in phase from one of said television fields to another, comprising: input means coupled to a source of incoming video information signals; input write clock means coupled to said input means for generating a write clock signal synchronized with said incoming video information; first sampling means coupled to said write clock for sampling said video information signal at a rate determined by said write clock signal prior to writing into said memory storage means, said input write clock means developing a ready-to-write signal at the completion of said sampling; said memory storage means having preassigned fixed burst phasing for each line store of said memory storage means; said signal processing means including means for developing a composite horizontal sync and burst timing control signal indicative of the timing of said incoming video signal and delay means responsive to said control signal for delaying said ready-to-write signal; output read clock means for generating a read clock signal; second sampling means coupled to output means and to said read clock for sampling said stored video information signals read out of said storage means, said output clock means developing a ready-to-read signal prior to said sampling; and memory control means coupled to said memory storage means and responsive to said ready-to-write and said ready-to-read signals for developing write and read memory storage control signals whereby only said active video image information portion is read into said memory storage means consistent with said preassigned fixed burst phasing.