Emitter ballast resistor configuration

Claim 2

In a semiconductor device which has a first semiconductor region of a first conductivity type extending from a principal surface into a semiconductor body, a second semiconductor region of a second conductivity type selectively formed within said first semiconductor region to be surrounded by the first semiconductor region and a third semiconductor region of the first conductivity type selectively formed within the second semiconductor region to be surrounded by the second semiconductor region as a collector region, a base region and an emitter region, respectively for said semiconductor device, said semiconductor device characterized in that said third semiconductor region includes a transistor operation portion, an electrode connection portion, and a ballast resistance portion located between said transistor operation portion and said electrode connection portion, wherein the lateral width of said second semiconductor region surrounding said ballast resistance portion is smaller than the lateral width of said second semiconductor region surrounding said electrode connection portion.

Claim 3

A semiconductor device according to claim 1, wherein electrodes are respectively on the surfaces of said transistor operation portion and said electrode connection portion.

Claim 4

A semiconductor device according to claim 1, wherein a fourth semiconductor region of said first conductivity type serving as an emitter region is selectively formed within said second semiconductor region in a manner to be spaced from said third semiconductor region, and said fourth semiconductor region includes a transistor operation portion, an electrode connection portion, and a ballast resistance portion located between said transistor operation portion and said electrode connection portion, and wherein the lateral width of said second semiconductor region surrounding said ballast resistance portion of said fourth semiconductor region is smaller than the lateral width of said second semiconductor region surrounding said electrode connection portion of said fourth semiconductor region.

Claim 5

A semiconductor device according to claim 3, wherein an electrode is on the surface of said second semiconductor region between said transistor operation portions of said third and fourth semiconductor regions.

Claim 6

In a semiconductor device which has a first semiconductor region of a first conductivity type extending from a principal surface into a semiconductor body, a second semiconductor region of a second conductivity type selectively formed within said first semiconductor region to be surrounded by the first semiconductor region, and a third semiconductor region of the first conductivity type selectively formed within said second semiconductor region to be surrounded by the second semiconductor region as a collector region, a base region and an emitter region, respectively for said semiconductor device, said semiconductor device characterized in that said third semiconductor region includes a pair of transistor operation portions separated from one another by a portion of said second semiconductor region, a pair of ballast resistance portions respectively coupled to said pair of transistor operation portions, said pair of ballast resistance portions being separated from one another by a portion of said second semiconductor region, and a common electrode connection portion coupled to said pair of ballast resistance portions, wherein a part of said first semiconductor region extends to said one principal surface of said semiconductor body between said ballast resistance portions so that the combined lateral width of said second semiconductor region surrounding said pair of ballast resistance portions is less than the total lateral width of said second semiconductor region surrounding said common electrode connection portion.

Claim 7

In a semiconductor device which has a first semiconductor region of a first conductivity type extending from a principal surface into a semiconductor body, a second semiconductor region of a second conductivity type selectively formed within said first semiconductor region to be surrounded by the first semiconductor region, and a third semiconductor region of the first conductivity type selectively formed within said second semiconductor region to be surrounded by the second semiconductor region as a collector region, a base region and an emitter region, respectively for said semiconductor device, said semiconductor device characterized in that said third semiconductor region includes a pair of transistor operation portions separated from one another by a portion of said second semiconductor region, a pair of ballast resistance portions respectively coupled to said pair of transistor operation portions, said pair of ballast resistance portions being separated from one another by a portion of said second semiconductor region, and a common electrode connection portion coupled to said pair of ballast resistance portions, wherein a part of said first semiconductor region extends to said one principal surface of said semiconductor body between said ballast resistance portions so that the combined lateral width of said second semiconductor region surrounding said pair of ballast resistance portions is less than the total lateral width of said second semiconductor region surrounding said common electrode connection portion.

Claim 8

A semiconductor device according to claim 5, wherein electrodes are respectively on the surface of said portion of said second semiconductor region between said transistor operation portions and on the surface of said common electrode connection portion.

Claim 9

A semiconductor device characterized in that a plurality of base regions are selectively formed to be separated from one another in a collector region, that a plurality of emitter regions each having an emitter ballast resistance portion are formed in said each base region, said each base region has a reduced lateral width surrounding said emitter ballast resistance portion, and that an electrode common to the respective emitter regions is formed.

Claim 10

A semiconductor device characterized in that a plurality of base regions are selectively formed to be separated from one another in a collector region, that a plurality of emitter regions each having an emitter ballast resistance portion are formed in said each base region, said each base region has a reduced lateral width surrounding said emitter ballast resistance portion, and that an electrode common to the respective emitter regions is formed.

Claim 11

A semiconductor device usable as a transistor wherein a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type selectively formed within the first semiconductor region and a third semiconductor region of the first conductivity type selectively formed within the second semiconductor region are respectively used as a collector region, a base region and an emitter region for said transistor, said semiconductor device characterized in that said third semiconductor region includes an original transistor operation portion, a terminal side portion, and a ballast resistance portion located between said original transistor operation portion and said terminal side portion, wherein said second semiconductor region includes a first base contact portion which is adjacent to said transistor operation portion and a second base portion adjacent to said ballast resistance portion, and further wherein the lateral width of said second base portion is less than the lateral width of said first base contact portion.

Claim 12

A semiconductor device usable as a transistor wherein a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type selectively formed within the first semiconductor region and a third semiconductor region of the first conductivity type selectively formed within the second semiconductor region are respectively used as a collector region, a base region and an emitter region for said transistor, said semiconductor device characterized in that said third semiconductor region includes an original transistor operation portion, a terminal side portion, and a ballast resistance portion located between said original transistor operation portion and said terminal side portion, wherein said second semiconductor region includes a first base contact portion which is adjacent to said transistor operation portion and a second base portion adjacent to said ballast resistance portion, and further wherein the lateral width of said second base portion is less than the lateral width of said first base contact portion.

Claim 13

In a semiconductor device which has a first semiconductor region of a first conductivity type extending from a principal surface into a semiconductor body, a second semiconductor region of a second conductivity type selectively formed in said first semiconductor region to be surrounded by the first semiconductor region and a third semiconductor region of the first conductivity type selectively formed in said second semiconductor region to be surrounded by the second semiconductor region as a collector region, a base region and an emitter region, respectively for said semiconductor device, said semiconductor device characterized in that said third semiconductor region includes a transistor operation portion, an electrode connection portion, and a ballast resistance portion located between said transistor operation portion and said electrode connection portion, wherein a parasitic transistor is formed by said electrode connection portion and said first and second semiconductor and wherein the lateral width of said second semiconductor region surrounding said ballast resistance portion is smaller than the lateral width of said second semiconductor region surrounding said electrode connection portion to provide a highly resistive base connection to said parasitic transistor.

Claim 14

In a semiconductor device which has a first semiconductor region of a first conductivity type extending from a principal surface into a semiconductor body, a second semiconductor region of a second conductivity type selectively formed in said first semiconductor region to be surrounded by the first semiconductor region and a third semiconductor region of the first conductivity type selectively formed in said second semiconductor region to be surrounded by the second semiconductor region as a collector region, a base region and an emitter region, respectively for said semiconductor device, said semiconductor device characterized in that said third semiconductor region includes a transistor operation portion, an electrode connection portion, and a ballast resistance portion located between said transistor operation portion and said electrode connection portion, wherein a parasitic transistor is formed by said electrode connection portion and said first and second semiconductor and wherein the lateral width of said second semiconductor region surrounding said ballast resistance portion is smaller than the lateral width of said second semiconductor region surrounding said electrode connection portion to provide a highly resistive base connection to said parasitic transistor.

Claim 15

A semiconductor device according to claim 1, 8 or 9, wherein the lateral width of said ballast resistance portion is less than the lateral width of said transistor operation portion.

Claim 16

A semiconductor device according to claim 1, 8 or 9, wherein the lateral width of said ballast resistance portion is equal to the lateral width of said transistor operation portion.

Claim 17

A semiconductor device according to claim 5, wherein the lateral widths of said ballast resistance portions are equal to the lateral widths of said transistor operation portions.

Claim 18

A semiconductor device according to claim 5, wherein the lateral widths of said ballast resistance portions are less than the lateral widths of said transistor operation portions.