Comparing input words to a word dictionary for correct spelling

Claim 2

In a text processing system including a mini-processor, a memory for storing instructions for controlling said mini-processor, and a dictionary memory for storing a representation for each word of a dictionary of correctly spelled words, apparatus for checking the spelling of input words by comparison to said dictionary of representations of correctly spelled words comprising: a source of input words connected to said mini-processor decode means connected to said mini-processor for converting each character of an input word into an output numerical representation; a magnitude table storage means addressably connected to said decode means for outputting a magnitude value corresponding to each numerical representation output by said decode means; a first adder means connected to said magnitude table storage means and said mini-processor for accumulating a magnitude sum of the magnitude values output by said magnitude table storage means and outputting said magnitude sum to said mini-processor for use as an address to access said dictionary memory; a second adder means connected to said decode means for accumulating partial sums of said numerical representations output by said decode means; binary table storage means connected to said second adder means for storing a plurality of binary numbers addressable to output one of said binary numbers for each partial sum accumulated by said second adder means; third adder means connected to said binary table storage means for accumulating a modulo-2 sum of the output of said binary table storage means; binary-to-decimal decode means connected to said third adder means and said mini-processor for converting the modulo-2 sum output of said third adder means from a binary number to a decimal angle value and outputting the result to said mini-processor; means for comparing said decimal angle value to the contents of said dictionary memory at the accessed address; means for indicating said input word is correctly spelled when said compare is equal; and means for indicating said input word is not correctly spelled when said compare is unequal.

Claim 3

The apparatus of claim 1 wherein said third adder means is an exclusive-OR.

Claim 4

In a text processing system including a mini-processor, a memory for storing instructions for controlling said mini-processor, and a dictionary memory for storing a representation for each text word of a dictionary of correctly spelled text words, apparatus for generating representations of input text words for comparison to said dictionary of correctly spelled words comprising: a source of input text words; decode means connected to said mini-processor for converting each character of an input text word into a numerical representation; a magnitude table storage means addressably connected to said decode means for storing a magnitude value corresponding to each numerical representation output by said decode means; a first adder means connected to said magnitude table storage means and said mini-processor for accumulating a magnitude sum of the magnitude values output by said magnitude table storage means and outputting said magnitude sum to said mini-processor for use as an address to said dictionary memory; a second adder means connected to said decode means for accumulating partial sums of said numerical representations output by said decode means; binary table storage means for storing a plurality of binary numbers and addressable to output said binary numbers; register means connected to said mini-processor for receiving from said mini-processor and storing a value representing the size of said binary table storage means; compare means connected to said second adder means and said register means for comparing each accumulated partial sum to the binary table storage means size value; gate means connected to said binary table storage means and said second adder means and operable by said compare means for accessing said binary table storage means at the address equal to said accumulated partial sum for a binary number when the accumulated partial sum is less than said binary table storage means size value; third adder means connected to said binary table storage means for accumulating a modulo-2 sum of the binary numbers output by said binary table storage means; binary to decimal decode means connected to said third adder means, and said mini-processor for converting the modulo-2 sum output of said third adder means from a binary number to a decimal angle value and outputting the result to said mini-processor; means for comparing said decimal angle value to the contents of said dictionary memory at the accessed address; means for indicating said input word is correctly spelled when said compare is equal; and means for indicating said input word is not correctly spelled when said compare is unequal.

Claim 5

In a text processing system including a mini-processor, a memory for storing instructions for controlling said mini-processor, and a dictionary memory for storing a representation for each text word of a dictionary of correctly spelled text words, apparatus for generating representations of input text words for comparison to said dictionary of correctly spelled words comprising: a source of input text words; decode means connected to said mini-processor for converting each character of an input text word into a numerical representation; a magnitude table storage means addressably connected to said decode means for storing a magnitude value corresponding to each numerical representation output by said decode means; a first adder means connected to said magnitude table storage means and said mini-processor for accumulating a magnitude sum of the magnitude values output by said magnitude table storage means and outputting said magnitude sum to said mini-processor for use as an address to said dictionary memory; a second adder means connected to said decode means for accumulating partial sums of said numerical representations output by said decode means; binary table storage means for storing a plurality of binary numbers and addressable to output said binary numbers; register means connected to said mini-processor for receiving from said mini-processor and storing a value representing the size of said binary table storage means; compare means connected to said second adder means and said register means for comparing each accumulated partial sum to the binary table storage means size value; gate means connected to said binary table storage means and said second adder means and operable by said compare means for accessing said binary table storage means at the address equal to said accumulated partial sum for a binary number when the accumulated partial sum is less than said binary table storage means size value; third adder means connected to said binary table storage means for accumulating a modulo-2 sum of the binary numbers output by said binary table storage means; binary to decimal decode means connected to said third adder means, and said mini-processor for converting the modulo-2 sum output of said third adder means from a binary number to a decimal angle value and outputting the result to said mini-processor; means for comparing said decimal angle value to the contents of said dictionary memory at the accessed address; means for indicating said input word is correctly spelled when said compare is equal; and means for indicating said input word is not correctly spelled when said compare is unequal.

Claim 6

The apparatus of claim 3 wherein said third adder means is an exclusive-OR.

Claim 7

The apparatus of claim 3 further including means connected to said second adder means and said register means and responsive to said compare means for subtracting said binary table storage means size value from said accumulated partial sum when said accumulated partial sum exceeds said binary table storage means size value to produce wrap-around of the address for accessing said binary table storage means.

Claim 10

The method of claim 6 wherein step (d) further includes the steps of: sequentially comparing the produced partial sum to a storage limit value for the binary storage device and subtracting said storage limit value from said partial sum when said partial sum exceeds said storage limit value to produce a partial sum less than the storage limit value effectively producing a wrap-around of the accessing of said binary storage device.